Notes on mixed signal programming

These are my notes on my upcoming book about mixed-signal programming.

Welcome to my virtual shack! I am ON4CKO, QTH Belgium.

Mixed signal is a hybrid analog-digital computer language. It is designed to be safer and faster than turing complete languages, like C, python,php ... The technique is rooted in the seventies and eighties, when analogue computing was more common.
Analogue computing allows complex problems to be modeled with an analogon. This is an electrical representation of a system; In contrast to digital algorithms that solve problems sequentially (step-by-step), the analogon is immediate.

Python is used here. The examples use decorators and generative functions. I use a modified version of gnucap as circuit simulator backend. A physical equivalent on raspberry pie is illustrated later in this text.

Below, a two resistor voltage divider with one parameter 'vin'. The voltage of this parameter is divided by two (VIN/2).

The analogon, the second part, has parameters: title, netlist, input signal(s), output signal(s) and mode: We select the 'operational' mode ("op") as opposed of the time-dependent "transient" mode.

The output is the voltage of node 2 - between the two resistors. It can be extracted using 'yield', or, you can use the shorthand version with function 'OP'. The first includes debug messages (constructor, alarm conditions, etc.).

Notice the parameters nodes and clk (clock). nodes contain a list of output signals to monitor and assert alarm conditions on the circuit BEFORE they are yielded in the main program. The clock (clk) is an integer, a count how much the circuit signals have been yielded.

The analogon has to return the input parameter vin ; Without this input power, the circuit triggers an alarm and halts.

# Floating point division: 12/2
R1 1 2 1k
R2 2 0 1k
V1 1 0 vin

@analogon("hello world",schematics,"vin","v(2)","op")
def divider(nodes,clk):
    return {"vin":12} 

# generative version  (incl. debugging)
div = divider  
yield( div )   # debug: building circuit hello world
yield( div )   # value: 6

# shorthand version
OP( divider )  # 6