## PIC Frequency Counter with Frequency Lock function

Written by: OH6CJ Osmo, January 13th, 2002, E-mail: [email protected]

 Table of Content: Frequency Reference Frequency Actual Subtraction and Comparator Digital Outputs Integrator Transistors Q2…Q4 Connection to Oscillator How to tune? PIC SW in the frequency counter Final test RB2 Function Is this worth to build it? Pictures are better readable locally with appropriate viewer, so we suggest download them first

This PIC software combines frequency counter and frequency lock functions. By adding couple of transistors and operation amplifier TL082, it is possible to lock the LC oscillator frequency.

Let’s look at the following block diagram. Software functions are presented inside the dashed area.

Figure 1.Block diagram of the frequency lock control.

### Frequency Reference

Frequency reference is formed from the measured frequency itself after the delay defined by parameter 0Dh, when the number of the consecutive samples (defined by 0Eh) of measured frequency are within the +/-20 Hz. Then the actual value is trigged as frequency reference until the SW detects that the lock conditions are not valid.

### Frequency Actual

Frequency actual is formed from the frequency counter function itself.

### Subtraction and Comparator

Frequency is measured every 100 ms. Next the frequency actual is subtracted from the reference and the difference is compared to value zero to calculate the deviation. If the result is zero, it means that no deviation and also no need to fine-tune the oscillator frequency.

If the result is negative it means that the frequency actual is higher than reference. This detects the direction of the needed frequency correction. Next the rough value of the difference is calculated. If within 20 Hz then only short 2.4 ms pulse is controlled. If bigger then 100 ms pulse is controlled. By means of these few calculations we have information how to fine-tune the frequency of the oscillator to hold the frequency actual equal as frequency reference. Simple, is it?

Figure 2. Control pulse length as a function of the frequency deviation.

### Digital Outputs

These pulses are controlled to digital outputs RB0 or RB3 according to the sign of the frequency difference. The outputs are never simultaneously on because it means almost short circuit.

Figure 3. Schematic diagram of the frequency counter and frequency lock circuit.

### Integrator

The controller is made using TL082 operation amplifier. The first amplifier is an integrator by means of the capacitor C8 and R23. A time constant is R23 * C8 = 22 M Ohms * 2.2 uF = 48 s. So the control is slow and it only fine tunes the oscillator frequency and this is of course the purpose of the controller. The VFO itself must be stable enough. Second amplifier of TL082 is connected as a buffer.

### Transistors Q2…Q4

If the PIC SW controls the output RB0 to state TRUE, then led D4 is light and Q2 saturates. It connects integrator input via R23 to GND and the voltage at the output pin 1 changes to positive direction. If the RB3 is controlled to state TRUE, D4 is light and Q3 connects the base of the Q4 to ground. As a result Q4 is saturated and +9 V is connected to the R23. Now output changes to negative direction. If none of RBs are controlled, the integrator acts an analogue memory. It holds the last value at the output. This suites well for the situation where the subtraction result of reference and actual is zero. The used transistor types are not critical.

### Connection to Oscillator

It must be added a capacitance diode connection to the oscillator circuit. See area A in the schematic diagram. This additional connection changes the frequency range of the oscillator. So it must be compensated by tuning the frequency range of VFO, if necessary. Output of the buffer amplifier (pin 7) is connected to the trimmer potentiometer R25. This is used to scale the effect of pulse to the oscillator frequency.

### How to tune?

1. First the oscillator must be temperature compensated so that after the “warming up” the frequency drift either stops or settle down to value e.g. 0…40 Hz / minute. Measure the frequency beginning of start and then follow the frequency with frequency counter. Note down the frequency e.g. every minute until the frequency has been settled down.

Figure 4. Frequency shift of my unstabilised colpitts oscillator.
2. Calculate the difference of frequencies between the start and when settled down. The range of the controller must be about double. Next test the effect of the capacitance diode circuit and change the C10 or D5 until you have enough range to change the oscillator frequency. See next test circuit.

Figure 5. Capacitance diode test circuit.

In my Colpitts oscillator 5…5.5 MHz the effect of the range was about +0.5 V…+7.5 V = = –15 kHz…+10 kHz.

3. Next test the printed board of frequency lock alone without connections to frequency counter or to the oscillator circuit. Connect wire from RB0 to X3 and RB3 to X4.
Connect +12 V to X2 and 0 V to X1 and voltage measurement to U5. The voltage should be about 9 V at the output of the regulator. Next connect measurement to U4 pin 7 to measure the output of the buffer amplifier. Connect only temporarily +9 V to terminal X3. Now the output voltage should be started to increase from the +4.5 V to positive direction. Disconnect the +9V from the terminal X3. Now the output voltage must be held to the last value. Test the X4 on the same way. Now the voltage must be changed to negative direction.

Figure 6. Printed board view from the component side.

Figure 7. Printed board view from the bottom side

### PIC SW in the frequency counter

Download the LCD4DIEP.HEX file or source code. It is compatible with LCD4DIEC.HEX concerning the frequency counter functions. See the parameter setting instructions from the LCD4DIEC document.

The configuration bits must be set:

Oscillator = XT, Watchdog Timer = OFF, Power Up Timer = OFF, Code Protect = OFF

Table 1. COUNTER MODE I/O functions when the freq_lock function is activated
(parameter 0BH = 0).

 COUNTER MODE I/O signal FALSE (0 V) TRUE (+5 V) RA2 input Sub Display Offset Add Display Offset RB0 input - Access to EEPROM MODE output - Increase Osc Freq RB1 input Display Offset1 Display Offset2 RB2 input - Freq_lock frozen RB3 output - Decrease Osc Freq

#### Parameters

Table 2. EEPROM-parameters 00h...0Fh functions

00h Display Offset 1 Highbyte High Byte Display Offset1   9001.50 kHz = 0DBC36 0Dh
01h Display Offset 1 Midbyte Mid Byte Display Offset1 BCh
02h Display Offset 1 Lowbyte Low Byte Display Offset1 36h
03h Display Offset 2 Highbyte High Byte Display Offset2 8998.50 kHz = 0DBB0A 0Dh
04h Display Offset 2 Midbyte Mid Byte Display Offset2 BBh
05h Display Offset 2 Lowbyte Low Byte Display Offset2 0Ah
06h Direct_frequency Direct frequency counting mode without sub or add functions = 00

Sub or add function activated = 01…FF

00h
07h EE_Fine1 Calibration value (1 == 3*4/fx = 3us) 15h
08h EE_Fine2 Calibration value (1 == 4*4/fx = 4us)

01h

09h

1x16_Display

LCD display type: 00 = 1x16 LCD, 01…FF = 2x20 LCD

01h

0Ah

Digits

01h

0Bh

#### Freq_lock_function

Activation of the Frequency Lock function.

00h = Function activated, 01…FFh = not activated

FFh

Ten_divider

Desimal point transfer one decade to right with external 10 divider HW.

00h = Function activated if 0Bh = 00h

01…FFh = not activated

FFh

0Dh

Delay_time_before_sampling

Delay time after the disconnection from the Locked state before the new sampling is started.

01h == 100 ms

32h = = 5 s.

0Eh

Sampling_time

Number of the consecutive samples in no locked state within the +/-20 Hz to set the measured frequency to reference. It is also the number of the consecutive samples in the locked state, which are out of the +/-100 Hz window to disconnect from the locked state.

01h = 1 sample (during 100ms)

05h
= = 5 samples

0Fh

EEPROM default values

If > 0 then default values are loaded on the next power-on.

00h

### Final test

If the previous tests and settings have been successfully performed, it is a time to do connections between the frequency counter and frequency lock printed boards as well as connections to the oscillator circuit.

Activate the Freq_Lock function by par. 0Bh. Reconnect the voltages to the boards and start to observe the LEDs D3 and D4. When the frequency reference has been sampled and set, the character “L” is displayed in the LCD. Observe the LEDs. Only short pulses should be seen seldom if there is a need to fine-tune the oscillator frequency. Long pulse can only been seen if the VFO drifts over 20 Hz within the 100 ms. A long pulse can be seen as a bright light (D3, D4) and short pulse as a dimmed one. The VFO that I have used in my transceiver, with the “warm” oscillator only few pulses can be seen during the 10-second period. At the beginning with “cold” VFO long pulses with short ones can also be seen.

The effect of the control is too big, if correction to one direction causes immediate correction to other direction. Then reduce the effect by turning R25 a bit to counter clockwise. If a long pulse lasts several seconds before out of lock situation, effect is too small. Turn the R25 a bit to clockwise.

It is good also to monitor the output voltage from the pin 7. The voltage should stay within the range of the amplifier output (about 0.5 V…7.5 V depending on the type of the used op. amplifier) so that minimum or maximum limit is never reached during the normal operation.

Conditions to go out of Lock State are the consecutive number of samples (0Eh) which are outside of +/-100 Hz window.

It is good to receive a stable carrier on the band and listen it when pulses are controlled. The audio frequency of the carrier must be remained stable. As well you can observe the stability of the 10 Hz decade in the LCD.

I have now tested this few months in my 80 m SSB/CW transceiver. I had to add a buffer amplifier using JFET to isolate the RF effect to the frequency measurement circuit. Otherwise during the transmit RF caused disturbation to the measurement.

### RB2 Function

A frequency lock function can be frozen with digital input RB2. How ever the last frequency reference is still set in the registers. This function can be used e.g. with direct conversion RX where TX offset is needed during the transmit period. A character “F” (Frozen) is displayed instead of “L” after the MHz text in the LCD display.

### Is this worth to build it?

Above all this software is as is. No guarantee for any functions. However I am satisfied for this SW and electronics. I don’t need a separate switch in the front panel to lock or unlock the frequency. This SW with HW does it automatically. Remember that this circuit does not repair a bad VFO at all, but with a good one, it compensates the long term drifting and makes it even better to use. It is nice to listen to the certain frequency on the band without continuous frequency corrections after a little while by means of the VFO knob.