SECTION 5

CIRCUIT DESCRIPTION

 

The 70-1336 unit is made up of three major sections: the RF section, the PA section, and the Logic Section.

RF SECTION

The RF Section consists of a frequency synthesizer, a transmit modulator, a receiver, and receive audio amplifier circuits.

SYNTHESIZER

Radio frequency signals for transmission and receiver injection are produced by voltage-controlled oscillators (VCO's) in a Phase-Lock Loop (PLL) configuration.

• Voltage Controlled Oscillators

In this radio, two VCO's are used — 0731 operates in transmit mode to generate transmit frequencies; Q711 operates in receive mode to generate receive injection frequencies. Each is buffered independently; by 0732 and Q712 respectively. Output of the buffers are amplified by 0131 and 0203 respectively. RF signal at receiver injection frequency (Fc + 45.0 MHz) is applied from the LO amplifier 0203 in the receiver circuit. RF signal from 0131 is amplified further by the PA portion.

When the frequency of the VCO output drifts away from the desired value, the loop adjusts the steering voltage to compensate.

A single VCO tank can tune across the entire 24 MHz channel spread. Only one of the two tanks is switched in at a time and they are selected by TXDL from the Logic portion. The microcomputer sets TXDL to logic low during transmit mode.

Resonance of each VCO tank is voltage-tuned by varactor diodes D711 and D731 respectively. Loop steering voltage applies reverse bias to all these varactor diodes simultaneously. As steering voltage increases, varactor diode capacitance decreases, so that net capacitance in each tank decreases, This increases resonant frequency of the tanks.

• Loop Dividers

The amplitude of the VCO signal from 0733 collector for TX and Q734 collector for RX is sufficient to feed prescaling frequency divider, IC771, which applies an output pulse once every 64 or 65 input cycles. Additional frequency division is also performed within IC771 to produce 2.5 kHz. X101 is a temperature-compensated crystal oscillator that produces a reference frequency of exactly 12.8 MHz. The reference frequency is divided by IC771 to produce 2.5 kHz, which is compared to the down-counted 2.5 kHz sample of VCO output. Normally the loop response is slowed enough by the active filter to block 5.0 kHz reference noise and prevent loop correction of voice modulation during transmit. Higher active filter rolloff frequency is selected by the microcomputer system on the Logic Board when the radio changes channels or it is keyed and unkeyed, by a logic low applied to the base of Q772. This increase in loop response speeds locking time.

A connection from an intermediate point in the phase/frequency comparator in IC771 is made at pin 7. When the loop is out of lock, the down-counted VCO sample is not in phase with the 2.5 kHz reference and low going pulses appear here, which produce a logic low at pin 7. This logic low is applied to Q778 and Q771 to switch to Q403-1/2 and Q504. Q504 then clamps off bias to transmit PA preamplifier Q501 to prevent errjission of erratic signals generated by the uncontrolled VCO.

• Modulator

Voice signals from the hand-microphone are applied to audio filter IC411, where frequency response is pre-emphasized and splatter filtered. Gain is such that stronger signals bring IC411 into clipping, which limits modulation. Harmonics above the 3 kHz modulation pass-band are removed by the 2.5 kHz pi-network in IC411. Modulation signals are then adjusted by RV403 so that modulation at limiting at IC407 will produce transmitted carrier deviation of ±5 kHz. Output of processed voice signals at IC411 pin 14 is fed to the gain control IC407.

 

RECEIVER

• Preselector

Through PIN-diode gates in the PA, RF signals are routed to the receiver input. Signals at image frequencies and frequencies far removed from the desired channel are rejected by a preselector comprised of sixtop-coupled, parallel tanks: L201,L202, L203, L204, L205, and L206. No tuning of these tanks is required for the entire 24 MHz channel frequency spread. Q201 provides adequate gain to overcome preselector signal losses and maximize receiver sensitivity.

• Injection

First Local Oscillator signal (channel frequency plus 45.0 MHz) is synthesized by the phase-lock loop and applied to Q203. A low pass filter is provided at the output of Q203; this rejects extraneous synthesized signals. No alignment for the first local oscillator signal is required.

• First Mixer

To maximize intermodulation immunity, a balanced configuration is used for the first mixer stage. High Injection is applied to L210-primary and preselector output is applied to its secondary center tap. A diode double balanced mixer using quad-diode D202 is employed. High injection is applied to the push-pull input of the mixer. Some of this signal appears at mixer output, but most is lost because L209 is designed to operate at the 45 MHz first IF frequency.

• First IF

Mixer output is applied to Q241, which drives L244. L244 tunes to match the input impedance of 45 MHz monolithic crystal filter FL241. L246 matches the output of FL241 to the input of FL242. FL241 and FL242 reject signals outside the channel bandwidth. L247 matches the output of FL242 to the input of Q242. Q242 amplifies the first IF signal at least 20 dB, and it is coupled to second IF IC241 by L248.

IC241 contains all second IF circuitry, a quadrature demodulator, and a threshold gate. X241 and circuitry in IC241 generate second LO injection 44.545 MHz. A double-balanced mixer, that cancels both input signals is used so that additional tuned circuits at its output are not needed. Mixer output signal of 455 kHz (IC241 pin 3) is bandpass filtered further by FL243 and FL244 then super-amplified (100+ dB) by the second IF amplifier/limiter within IC241 (pin 5).

• Demodulation

The quadrature detector in IC241 is another double-balanced mixer to which limiter output is applied. Its second input is taken from 455 kHz tank L250, which is also fed with limiter output (IC241 pin 7). Frequency deviation from carrier center will cause phase difference between the two demodulator input, which produces output. Preamplified recovered audio appears at demodulator output, pin 9. C264, C265, and L251 attenuate signals above 100 kHz.

• Audio

Recovered audio from IC241 is routed to op amp IC411, and applied to volume control RV301. Output of the RV301 is applied to the squelch gate 0408, then to audio amp IC406. Power Amplifier IC406 amplifiers the audio signal and drives the speaker.

• Squelch

Audio signals at lowpass filter L251 are routed through Squelch Range RV241, which calibrates squelch-break level when the side panel squelch switch is on. Signals at RV241 top feed a two-tank 60 kHz filter. The resulting 60 kHz signal is amplified by IC241 and Q244, then rectified by D243 to produce a DC voltage that varies inversely with received RF-carrier level. When the squelch switch is in the off position, it sinks all current from D243 so that squelch is open. When the squelch switch is in the on position, RV241 and a temperature-compensated circuit made up of R271, R272, and R273 limits the current from D243 to set a squelch threshold of 0.2ft V. The DC voltage is input to a level detector within IC241 and detector output is an open collector that sinks voltages to logic low when on-channel receiver input is above the squelch threshold established by RV241. Level detector output is applied through NSQ, the interconnect to microcomputer input port pin 58, so that the microcomputer can take appropriate action.

 

30-WATT PA SECTION

RF POWER AMPLIFIER

A PC-board stripline is used to match the base of Q501 to the coax. RF impedance at the collector of Q501 is transformed by PC-board stripline to the base terminal of driver Q502 and the collector of Q502 is transformed to the base of Q503. RF impedance at the collector of final-stage Q502 is again transformed by PC stripline and fine-tuned by CV501 match circuit impedance at RF-gate D501. L514—L517 and C515—C519 comprise the harmonic filter. R512 and R513 serve to drain static and other DC potentials from the antenna.

ANTENNA GATE

In receive mode, PIN diodes D501, D503 and D504 are unbiased. The RF signal path from the final amplifier Q503 is severed, and the impedance matching network consisting of L518, C520, C521, L509, and L522 routes signals from the antenna to the receiver input through 50 Ohm coax at J501.

D501, D503 and D504 are biased on in transmit mode. The receiver port network (L518 etc.) is detuned so that it appears as a high impedance to the antenna, and D501 couples final amplifier output to the antenna at J501.

AUTOMATIC POWER CONTROL

A PC stripline ahead of the harmonic filter, and a thin PC runner adjacent to it, serves as a directional coupler. D502 rectifies a small RF sample that is developed across the thin runner, producing a DC voltage that increases with RF power traveling forward into the antenna. This power level sensing voltage is applied to the inverting input of the comparator IC405 pin 6. The reference voltage applied to the comparator IC405 pin 5 is fed from RV402.

Output of the comparator IC405 is applied to Q504 via Q403, which is a current source that feeds primary DC to the collector circuits of predriver Q501.

The feedback loop, from the directional coupler to Q504 via the comparator input IC405 pin 6 holds RF output power at the constant level determined by the reference voltage of IC405 pin 5, which is initially adjusted using RV402.

 

LOGIC SECTION

MICROCOMPUTER

Radio operation is under control of a microcomputer system located on the Logic Board. This system is comprised of Microcomputer IC901 and 2K EEPROM IC903.

All CPU activity is performed step-by-step in time with a clock. The frequency of the clock is fixed by crystal X901. Because of the high clock speed, microcomputer activity seems instantaneous.

• Display and Switches

Pressing S305 (UP) or S307 (DN) applies a logic low to pin 56 or 55 of IC901, respectively. IC901 interprets this request as a channel change up or down and outputs the appropriate BCD display data from pin 13—pin 16 (DSPS—DSPO), which is applied to the BCD-to-Seven Segment Display driver, IC301. The channel display data is latched into IC301 by the DSP STB from pin 12 of IC901 via Q301. Once latched, the appropriate channel is diplayed on the channel display, D3C2.

Pressing S301 (MON) applies a logic low to pin 50 of IC901. IC901 responds by putting CTCSS/DCS decode in the monitor state and outputs a logic high from pin 13 (DSPS) which is latched in IC302 by the LED STB sent from pin 11. The logic high is inverted by Q302-2/2 to light the MON LED, D304.

Pressing optional switch S303 (PSCAN) applies a logic low to pin 51 of IC901. IC901 places the radio in the scan mode and indicates this by outputting a logic high from pin 16 (DSPO) which is latched into IC302 by the LED STB sent from pin 11. The logic high is inverted by Q302-1/2 to light the optional PSCAN LED, D305.

During transmit, TX 9V is present at the anode of D701, which applies a positive voltage to the anode of the TX LED, turning it on.

When a signal is received, Q410 is turned on, which allows a positive voltage to be applied to the anode of the BUSY LED via D401 -3/3

• CTCSS/DCS Encode/Decode

IC901 controls CTCSS/DCS encode and decode. In receive mode, the receive audio signal is high-pass filtered at IC50 to remove the CTCSS/DCS tones/codes. The CTCSS/DCS square wave is input through the Signal I/O line, pin 8 of IC901. IC901 determines if the CTCSS/DCS signal received is a valid tone/code. If it is valid, the output at pin 21 (MUTE) will go to logic high, which opens radio squelch.

In TX mode, pin 8 of IC901 will output the programmed CTCSS/DCS tone/code. TXDL goes low, turning off Q1, which turns on IC2-2/4 and IC2-4/4, allowing the tone/code on the Signal I/O line to pass thorugh IC1. IC1 is a programmable filter that "cleans up" CTCSS/DCS tones/codes. The generated tone is applied to Level Adjust RV1, and from there to Balance Control RV401 via C6. The signal is then sent to IC411 -3/4, where it is mixed with the mic audio, and also to D102 in the reference oscillator.

• RX and TX Switching

In receive mode, TXDL (pin 33 of IC901) is at logic high. This turns Q705 on, which causes Q702-1/2 to turn on. This applies RX8V to the VCO. Also, when TXDL is high, Q703-1/2 turns on, and Q703-2/2 turns off. This turns Q702-2/2 and 0704 off, which turns TX8V and TX9V off.

In transmit mode, TXDL is at logic low. This turns Q703-1/2 off, which turns Q703-2/2 on. This turns Q702-2/2 and Q704 on, which turn TX8V and TX9V on. Also, when TXDL is low, this turns Q705 off, which causes Q702-1/2 to turn off. This turns RX8V off, and TX8V and TX9V on.

• Data Control

When the radio is turned on, the contents of EEPROM IC903 are serially clocked into IC901 so that it can set up receiver frequency, scan operation, transmit/receive hold timer, busy-channel lock-out timer, time-out-timer and reference oscillator frequency control.

When a channel is changed, or when PTT is pressed, the contents of EEPROM IC903 are sent to IC901. IC901 then uses this data to send the appropriate information for the channel selected to IC771, CTCSS/DCS circuitry, display circuitry, and any signalling options.

• Reference Oscillator Frequency Control

The resistance of thermistor R107 varies with temperature. This resistance change is converted to a voltage by IC405, Output of IC405 is sent to IC901 pin 59 (TEMP). IC901 compares this data internally with the preset crystal type and programmed offset, and outputs a compensating voltage from pin 60 (F CONT). This voltage is sent to varactor diode D101 to stabilize the frequency of the reference oscillator.

DC POWER AND RESET

5 V DC power to all logic circuitry in the Logic portion is supplied from switched 13.6 V and is regulated by IC402. Microcomputer IC901 is power by the 5 V drop across D903, which is sourced by IC401 9 V regulator supply.

 

Table 5-1 — IC901 PINOUTS

Pin No. Pin Name I/O Flow Function Label Logic & Function
1 P37 I PORTS Programmer Interface
2 P36 O PCCTS Programmer Interface
3 P35 O PCRD Programmer Interface
4 P34 I PCSD Programmer Interface
5 P33 I PC CD Programmer Interface
6 P32 O BEEP Beep Tone Output
7 P31 0 CLK Clock Output for CTCSS/CDCSS
8 P30 I/O SIGNAL IO Signal I/O for CTCSS/CDCSS
9 P57 O LEDCHK LED Check Output
10 P56 O LEDAUX not used
11 P55 O LED STB Paralled-Data Strobe for Indicators
12 P54 0 DSP STB Parallel Data Strobe for Displays
13 P53 O DSPS Display/LED Data
14 P52 O DSP2 Display/LED Data
15 P51 O DSP1 Display/LED Data
16 P50 O DSPO Display/LED Data
17 P67 O AUXOUT Aux Switch Output (Low = ON)
18 P66 I TASW Talk-around Switch Input (Low = ON)
19 P65 O SCRB STB Serial Data Strobe for Voice Scrambler
20 P64 0 AUX STB Serial Data Strobe for AUX
21 P63 0 MUTE Low = MUTE
22 P62 I HANGUP Low = HANG UP
23 P61 I PTT Low = TX
24 P60 I VLINT Low = LOW VOLTAGE
25 R/W O — not used
26 SYNC. 0 — not used
27 CNVss I — GND
28 RESET I — Low = MICROCOMPUTER RESET
29 XlN I — Crystal Oscillator, 8 MHZ
30 xout O — Crystal Oscillator, 8 MHz
31 0 O — not used
32 Vss I — GND
33 P27 O TXDL Low = TX ACTIVATE
34 P26 O DA STB Serial Data Strobe for D/A Converter
35 P25 O VCOCHG VCO Switch Signal Output
36 P24 O LPSW Loop Switch Signal Output
37 P23 I/O PLCL Synth Unlock (Low = UNLOCK)
38 P22 O DSTB Serial Data Strobe for Synthesizer
39 P21 O DCLK Clock for Serial Data
40 P20 O DATA Serial Data Output
41 P17 I/O — not used
42 P16 I/O — not used
43 P15 I/O — not used
44 P14 I/O — not used
45 P13 I/O CS1 Chip Select for EEPROM
46 P12 0 SK Clock for EEPROM
47 P11 O Dl Data Input into EEPROM
48 P10 DO Data Output from EEPROM
49 P07 AUXSW/CHO AUX Switch (Low = ACTIVE)/CHNL NO, INPUT
50 P06 MONSW/CH1 Monitor Switch (Low = ACTIVE)/CHNL NO. INPUT
51 P05 P.SCAN/CH2 PRI Switch (Low = ACTIVE)/CHNL NO. INPUT
52 P04 SCNSW/CH3 SCAN Switch (Low = ACTIVE)/CHNL NO. INPUT
53 P03 DEPWRSW/CH4 DE-POWER Switch (Low = ACTIVE)/CHNL =NO. INPUT
54 P02 — /CH5 not used/CHNL NO. INPUT
55 P01 DNSW/CH6 DOWN Switch (Low = ACTIVE)/CHNL NO. INPUT
56 POO UPSW/CH7 UP Switch (Low = ACTIVE)/CHNL NO. INPUT
57 P42 VLTIN not used
58 P41 NSQIN NSQ Status Input (High = RECEIVE)
59 P40 TEMP Thermal Sensor Input
60 DA2 O FCONT Reference Frequency Control Output
61 DA1 O — not used
62 VREF — Reference Voltage Input to Convert A/D
63 AVSS — GND
64 VCC — +5 V