JFET BIASING BASICS
By Steve Ratzlaff
You might want to know how to bias a JFET so you can adjust the bias easily. JFETs vary considerably in their Idss, even from a handful of the same type of JFET; that's the nature of the JFET. The manufacturer can screen them for Idss and give them a separate part number, like the 2N5486 series does--they just take a huge batch and sort them for Idss and then mark them accordingly.
You can test a JFET's Idss very simply by putting a current meter in series with drain lead, shorting gate to source, and VERY BRIEFLY connect the Vcc supply (set at the desired operating voltage--is best to start at ~9-12volts, if higher Vcc is contemplated. Low current JFETs won't be destroyed by more than several seconds of this; simply monitor until the current is more or less steady. It can continually creep higher and higher, in this case, feel the case, if it's hot or very hot, STOP THE TEST IMMEDIATELY!
You can measure Idss of most JFETS, but the J308, 309 and 310 (and U310 etc) family will heat up and destroy itself if you let unrestrained drain current go for more than several seconds; the factory determines Idss for these with a pulse test.)
So, that's why a bias adjust is practically mandatory when playing with JFETs in a common source type of configuration. And for my particular whipamp circuit, the JFET bias is adjusted for minimum distortion products when the final whipamp is being adjusted on the bench, using a 2-tone IMD distortion test setup.
This is the method I use in my active amp JFET frontend. First, a word schematic of the JFET circuit.
I use a source follower. The gate resistor to ground is 10M (it can be most any value from 1-10M, the actual input impedance will be quite a bit lower. Use a nominal 10K pot, with one end to ground, the other end to Vcc. From the pot wiper insert a 2.2M resistor (value not critical, should be fairly high), the other end goes to the JFET gate. The wiper can be decoupled to ground with a 0.1uF cap if desired, but it's not really necessary.
The JFET drain needs to be very well decoupled to ground with a 0.1uF good-quality short-lead cap as close to the drain as possible or practical. This is very important, specially for RF JFETs, to minimize any tendency for instability. The pot can then be set for the desired JFET current, monitored by the voltage across the source. I forget which position of the pot sets the current to the max, to be safe, set the pot to midposition.
J310's can have 20-30mA drain current as their max current spec (known as "Idss", drain current with gate shorted to source)--of course normally you never run them at max current.
Theory says the noise figure of a JFET is the lowest when run at its Idss, but in practice usually the JFET is not run at Idss, especially power ones like the J310, without some type of heat sinking. If your JFET is a 1-5mA device, then it could safely be run at its Idss.
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