/*****************************************************************************/

/*
 *	sm_afsk1200.c  -- soundcard radio modem driver, 1200 baud AFSK modem
 *
 *	Copyright (C) 1996  Thomas Sailer (sailer@ife.ee.ethz.ch)
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *  Please note that the GPL allows you to use the driver, NOT the radio.
 *  In order to use the radio, you need a license from the communications
 *  authority of your country.
 *
 *  (Previously uncommented code documented September 1999 by KD6PAG
 *  <kd6pag@qsl.net> to reflect a careful study of the code.  Code is
 *  unchanged but comments may contain inaccuracies.  Any corrections
 *  or suggestions gratefully accepted.)  
 */

#include "sm.h"
#include "sm_tbl_afsk1200.h"

/* --------------------------------------------------------------------- */

struct demod_state_afsk12 {
	unsigned int shreg;
	unsigned int bit_pll;
	unsigned char last_sample;
	unsigned int dcd_shreg;
	int dcd_sum0, dcd_sum1, dcd_sum2;
	unsigned int dcd_time;
	unsigned char last_rxbit;
};

struct mod_state_afsk12 {
	unsigned int shreg;
	unsigned char tx_bit;
	unsigned int bit_pll;
	unsigned int dds_inc;
	unsigned int txphase;
};

/* --------------------------------------------------------------------- */

/*
 * Phase increments for low and high AFSK frequencies
 */
static const int dds_inc[2] = { 
	AFSK12_TX_FREQ_LO*0x10000/AFSK12_SAMPLE_RATE,
	AFSK12_TX_FREQ_HI*0x10000/AFSK12_SAMPLE_RATE 
};

/*
 * Fill buffer with audio samples by doing conventional [co]sine wave
 * synthesis.  This is the 8 bit version.
 *
 * If you change this one, make sure you update modulator_1200_s16()
 */
static void modulator_1200_u8(struct sm_state *sm, unsigned char *buf, 
			      unsigned int buflen)
{
	/* Setup pointer to transmit state for clarity and speed */
	struct mod_state_afsk12 *st = (struct mod_state_afsk12 *)(&sm->m);

	/* Fill buffer with 8 bit samples */
	for (; buflen > 0; buflen--) {
		/* Is it time to pick up another bit? */
		if (!((st->txphase++) & 7)) {
			/*
			 * If there are none left in the shift register, pick
			 * up another byte and insert the empty marker bit.
			 * (n.b. hdlcdrv_getbits() is an in-line function.)
			 */
			if (st->shreg <= 1)
				st->shreg = hdlcdrv_getbits(&sm->hdrv) | 0x10000;
			/* Toggle output if low bit of shift is zero */
			st->tx_bit = (st->tx_bit ^ (!(st->shreg & 1))) & 1;

			/* Shift out that data bit */
			st->shreg >>= 1;
		}
		/* Choose a phase increment for DDS oscillator per data bit */
		st->dds_inc = dds_inc[st->tx_bit & 1];

		/* Get sample from unsigned cos() table and advance phase */
		*buf++ = OFFSCOS(st->bit_pll);
		st->bit_pll += st->dds_inc;
	}
}

/* --------------------------------------------------------------------- */

/*
 * Fill buffer with audio samples by doing conventional [co]sine wave
 * synthesis.  This is just like the 8 bit version except it's 16 bits.
 *
 * If you change this one, make sure you update modulator_1200_s8()
 * Only differences are commented below.
 */
static void modulator_1200_s16(struct sm_state *sm, short *buf, unsigned int buflen)
{
	struct mod_state_afsk12 *st = (struct mod_state_afsk12 *)(&sm->m);

	/* Fill buffer with 16 bit signed samples */
	for (; buflen > 0; buflen--) {
		if (!((st->txphase++) & 7)) {
			if (st->shreg <= 1)
				st->shreg = hdlcdrv_getbits(&sm->hdrv) | 0x10000;
			st->tx_bit = (st->tx_bit ^ (!(st->shreg & 1))) & 1;
			st->shreg >>= 1;
		}
		st->dds_inc = dds_inc[st->tx_bit & 1];

		/* Get sample from signed cos() table, not unsigned table. */
		*buf++ = COS(st->bit_pll);
		st->bit_pll += st->dds_inc;
	}
}

/* ===================================================================== */

/*
 * Convolve incoming signal with fixed waveform.  Incoming signal is in
 * unsigned 8-bit format.  This is open coded, so if 'coeff' is a fixed
 * address, indexing will not be necessary.
 */
extern __inline__ int convolution8_u8(const unsigned char *st, const int *coeff, int csum)
{
	/* Account for DC offset in sign vs. unsigned input [?] */
	int sum = -0x80 * csum;
	
	sum += (st[0] * coeff[0]);
	sum += (st[-1] * coeff[1]);
	sum += (st[-2] * coeff[2]);
	sum += (st[-3] * coeff[3]);
	sum += (st[-4] * coeff[4]);
	sum += (st[-5] * coeff[5]);
	sum += (st[-6] * coeff[6]);
	sum += (st[-7] * coeff[7]);

	sum >>= 7;
	return sum * sum;
}

/*
 * Convolve incoming signal with fixed waveform.  Incoming signal is in
 * signed 16-bit format.  This is alos open coded, so if 'coeff' is a 
 * fixed address, indexing will not be necessary on the coefficients.
 */
extern __inline__ int convolution8_s16(const short *st, const int *coeff, int csum)
{
	int sum = 0;
	
	sum += (st[0] * coeff[0]);
	sum += (st[-1] * coeff[1]);
	sum += (st[-2] * coeff[2]);
	sum += (st[-3] * coeff[3]);
	sum += (st[-4] * coeff[4]);
	sum += (st[-5] * coeff[5]);
	sum += (st[-6] * coeff[6]);
	sum += (st[-7] * coeff[7]);

	sum >>= 15;
	return sum * sum;
}

/*
 * Convolve incoming signal with sine waves representing low and high
 * frequencies of AFSK signal (1200 Hz vs. 2200 Hz).  Result is a signed
 * integer, the sign of which determines which bit and the magnitude the
 * quality of the signal.
 *
 * This is open coded, and will turned into approximately 64 add/multiply
 * on the signal, plus another dozen or so on the result.  The coefficients
 * are at fixed addresses, so the only indexing will be done on the data.
 */
extern __inline__ int do_filter_1200_u8(const unsigned char *buf)
{
	/* 
	 * Convolve complex sine wave representing low tone with incoming
	 * signal and sum the square of the results.
	 */
	int sum = convolution8_u8(buf, afsk12_tx_lo_i, SUM_AFSK12_TX_LO_I);
	sum += convolution8_u8(buf, afsk12_tx_lo_q, SUM_AFSK12_TX_LO_Q);
	/* 
	 * Convolve complex sine wave representing high tone with incoming
	 * signal and subtract the square of the results.  The end result
	 * allows us to make a decision between ones and zero simply on
	 * the basis of the sign of the result.
	 */
	sum -= convolution8_u8(buf, afsk12_tx_hi_i, SUM_AFSK12_TX_HI_I);
	sum -= convolution8_u8(buf, afsk12_tx_hi_q, SUM_AFSK12_TX_HI_Q);
	return sum;
}

/* 
 * Exactly the same as the previous routine except that samples are in
 * 16 bit signed instead of 8 bit unsigned format.
 */
extern __inline__ int do_filter_1200_s16(const short *buf)
{
	int sum = convolution8_s16(buf, afsk12_tx_lo_i, SUM_AFSK12_TX_LO_I);
	sum += convolution8_s16(buf, afsk12_tx_lo_q, SUM_AFSK12_TX_LO_Q);
	sum -= convolution8_s16(buf, afsk12_tx_hi_i, SUM_AFSK12_TX_HI_I);
	sum -= convolution8_s16(buf, afsk12_tx_hi_q, SUM_AFSK12_TX_HI_Q);
	return sum;
}

/* --------------------------------------------------------------------- */

/* 
 * Phase offsets in phase locked loop depending on lateness or earliness 
 * of bit transition.  Phase is in the low order 16 bits.
 */
static const int pll_corr[2] = { -0x1000, 0x1000 };

/*
 * Demodulate 1200 AFSK signal by convolving with two complex sine waves,
 * representing low and high frequencies of AFSK signal (1200 Hz vs. 2200 Hz).
 * Note that we're examining the sign of the sum of the squares of the results
 * of convolution.  This done on a per-sample basis to detect bit transitions
 * and extract clock signals thereby.  This might be overkill, but we're only
 * running at 9600 samples/second, so it's not that bad on a modern processor.
 *
 * If you change this one, make sure you update demodulator_1200_s16()
 */
static void demodulator_1200_u8(struct sm_state *sm, const unsigned char *buf, unsigned int buflen)
{
	/* Setup pointer to transmit state for clarity and speed */
	struct demod_state_afsk12 *st = (struct demod_state_afsk12 *)(&sm->d);
	int j;
	int sum;
	unsigned char newsample;

	/*
	 * Process buffer on per-sample basis.
	 */
	for (; buflen > 0; buflen--, buf++) {
		/* 
		 *
		 * Note that we don't run off the beginning of the buffer 
		 * we are supplied a buffer which includes an overlap given
		 * in &sm_afsk1200_rx (see below).
		 *
		 * do_filter...() functions are open coded, so this is where
		 * the bulk of the work is done in this loop.
		 */
		sum = do_filter_1200_u8(buf);

		/* Advance shift register used to determine signal quality */
		st->dcd_shreg <<= 1;

		/* Advance phase used to determine bit cells. */
		st->bit_pll += 0x2000;

		/* Current estimate of whether this is a one or a zero. */
		newsample = (sum > 0);

		/* 
		 * If this is a bit transition, then adjust signal quality
		 * and make adjustments to phase lock loop.
		 */
		if (st->last_sample ^ newsample) {
			/* Mark transitions in shift register */
			st->last_sample = newsample;
			st->dcd_shreg |= 1;

			/* 
			 * Advance or retard phase slightly according to
			 * whether this transition seems early or late.
			 */			   
			st->bit_pll += pll_corr
				[st->bit_pll < 0x9000];

			/*
			 * Inline hweight functions compute the number of
			 * bits present.  Look for expected transitions vs.
			 * unexpected transition.
			 */
			j = 4 * hweight8(st->dcd_shreg & 0x38)
				- hweight16(st->dcd_shreg & 0x7c0);
			st->dcd_sum0 += j;
		}
		/* Record transitions for debugging (conditionally compiled) */
		hdlcdrv_channelbit(&sm->hdrv, st->last_sample);

		/* Update DCD state periodically */
		if ((--st->dcd_time) <= 0) {
			hdlcdrv_setdcd(&sm->hdrv, (st->dcd_sum0 + 
						   st->dcd_sum1 + 
						   st->dcd_sum2) < 0);
			st->dcd_sum2 = st->dcd_sum1;
			st->dcd_sum1 = st->dcd_sum0;
			st->dcd_sum0 = 2; /* slight bias */
			st->dcd_time = 120;
		}
		/* Have we completed a bit cell? */
		if (st->bit_pll >= 0x10000) {
		        /* Yes, wrap the phase, advance the shift register */
			st->bit_pll &= 0xffff;
			st->shreg >>= 1;

			/* We have a '1' if there was a bit transition. */
			st->shreg |= (!(st->last_rxbit ^
					st->last_sample)) << 16;

			/* Remember the last state so we can see transitions */
			st->last_rxbit = st->last_sample;

			/* Maybe reset pointer into diagnostic buffer */
			diag_trigger(sm);
			if (st->shreg & 1) {
				hdlcdrv_putbits(&sm->hdrv, st->shreg >> 1);
				st->shreg = 0x10000;
			}
		}
		/* 
		 * Maybe record 'sum' for debugging (see "sm.h" for details),
		 * saving it in 16 bit signed format
		 */
		diag_add(sm, (((int)*buf)-0x80) << 8, sum);
	}
}

/* --------------------------------------------------------------------- */


/*
 * Exactly the same as the previous routine except that samples are in
 * 16 bit signed instead of 8 bit unsigned format.
 *
 * If you change this one, make sure you update demodulator_1200_s8()
 * Only differences are commented below.
 */
static void demodulator_1200_s16(struct sm_state *sm, const short *buf, unsigned int buflen)
{
	struct demod_state_afsk12 *st = (struct demod_state_afsk12 *)(&sm->d);
	int j;
	int sum;
	unsigned char newsample;

	for (; buflen > 0; buflen--, buf++) {
		/* Process 16 bit signed samples (instead of 8 bit unsigned) */
		sum = do_filter_1200_s16(buf);
		st->dcd_shreg <<= 1;
		st->bit_pll += 0x2000;
		newsample = (sum > 0);
		if (st->last_sample ^ newsample) {
			st->last_sample = newsample;
			st->dcd_shreg |= 1;
			st->bit_pll += pll_corr
				[st->bit_pll < 0x9000];
			j = 4 * hweight8(st->dcd_shreg & 0x38)
				- hweight16(st->dcd_shreg & 0x7c0);
			st->dcd_sum0 += j;
		}
		hdlcdrv_channelbit(&sm->hdrv, st->last_sample);
		if ((--st->dcd_time) <= 0) {
			hdlcdrv_setdcd(&sm->hdrv, (st->dcd_sum0 + 
						   st->dcd_sum1 + 
						   st->dcd_sum2) < 0);
			st->dcd_sum2 = st->dcd_sum1;
			st->dcd_sum1 = st->dcd_sum0;
			st->dcd_sum0 = 2; /* slight bias */
			st->dcd_time = 120;
		}
		if (st->bit_pll >= 0x10000) {
			st->bit_pll &= 0xffff;
			st->shreg >>= 1;
			st->shreg |= (!(st->last_rxbit ^
					st->last_sample)) << 16;
			st->last_rxbit = st->last_sample;
			diag_trigger(sm);
			if (st->shreg & 1) {
				hdlcdrv_putbits(&sm->hdrv, st->shreg >> 1);
				st->shreg = 0x10000;
			}
		}
		/* Record 'sum' for debugging (no conversion necessary here) */
		diag_add(sm, *buf, sum);
	}
}

/* --------------------------------------------------------------------- */

static void demod_init_1200(struct sm_state *sm)
{
	struct demod_state_afsk12 *st = (struct demod_state_afsk12 *)(&sm->d);

       	st->dcd_time = 120;
	st->dcd_sum0 = 2;	
}

/* --------------------------------------------------------------------- */

const struct modem_tx_info sm_afsk1200_tx = {
	"afsk1200", sizeof(struct mod_state_afsk12), 
	AFSK12_SAMPLE_RATE, 1200, modulator_1200_u8, modulator_1200_s16, NULL
};

const struct modem_rx_info sm_afsk1200_rx = {
	"afsk1200", sizeof(struct demod_state_afsk12), 
	AFSK12_SAMPLE_RATE, 1200, 8, AFSK12_SAMPLE_RATE/1200, 
	demodulator_1200_u8, demodulator_1200_s16, demod_init_1200
};

/* --------------------------------------------------------------------- */