Design
The first step taken in
implementing the
eta, and Ege.
From The equations described in
the
Given
the Mosis 0.18 process parameters, the Vptat voltage required is 600mV.
The
resistor values required are calculated from the Vptat
and delta Vbe.
This bandgap requires two lateral PNP transistors. Actually,
it requires 48 lateral transistors in parallel. The Mosis 0.18
micron process does not support lateral PNPs
directly. One has to use a MOS transistor operated as a lateral bipolar
[10]. This lateral bipolar requires
special care in layout. The actual layout of the lateral PNP is shown in
figure 1. Unfortunately, there are two parasitic vertical PNPs that are also present in the layout. These
vertical transistors cause a leak into the substrate, which could effect
the output of the bandgap. I spent significant amount of time trying to
determine the effects of this by using the lateral PNP models from [11].
Figure
1
Because
the gates of the M7 and M10 in the schematic are in an unknown state when
the bandgap powers up, a startup circuit is
required. The startup circuit was actually the more difficult part of the
design. Because the Mosis 0.18u process design
rules have restrictions on mosfet length minimum
and maximum ratios, creating the weak pull-up transistor was a challenge.
The startup circuit is basically a pseudo nmos
inverter. When the bandgap initially is powered,
the weak pull-up transistor drives the gate voltage of Msu2 high turning
Msu2 on. The current through Msu2 pulls the gates of the current mirrors of
the bandgap down, forcing the current mirrors on.
The output voltage then starts to rise. Once the output reaches the trigger
level of the inverter, the inverter output goes low. This shuts off the
current in Msu2. By this time the current mirrors are sustaining their own
currents. The simulation plots in Fig. 2. Show the startup circuit in
action. The spike on the graph of N4 is startup circuit energizing the bandgap. Onc can observe the
VREF voltage jumping after the N4 spike. The bandgap
could start up without the startup circuit, but this would be a game of
chance.
Figure
2
A plot of the output vs.
temperature is shown in figure 3. You can see that the bandgap
is only accurate near T=300K as theory would predict.
The
layout of a bandgap is more demanding than that of say a digital core. All
the transistors need to be matched as closely as possible. Variations in
production can cause mismatches in transistors that translate into
effecting the temeprature independance of the output. To improve transistor
matching dummy poly, dummy tansistors, and common centrioding techniques
were used.
As an
examplein figure 5, an extra ring of bipolar transistors was added around
the 7x7 array of bipolars to protect the itransistors inside the ring from
procsses variations.
I
also had to create my own analog ESD pads for the Mosis 0.18 process. Mosis
had not yet released a pad library for this process. I took the Mosis pad
library from the 0.25 process and made changes. Because this is from a
larger process almost all the design rules were satisfied. The one major
exception was the via and contact sizes. So, I exported the pad layouts to
the CIF format, and read the file with the emacs editor. Using automatic
search and replace, I replaced the via and contacts with new vias and
contacts of the correct size. Once complete there were few remaing DRC
errors left in the PADS that had to be corrected manually.
