GW6BWX Low Cost Testcard Generator

Inside this box is the GW6BWX Low Cost Testcard Generator. On the front of the box is, from top to bottom, Video out, page selector, on/off switch and power. It fits inside a box designed for remote controls, this has a battery compartment that will allow the use of a 9V PP3 for portable operations.

The Test Card Generator was first discribed in CQTV201 by Brian, GW6BWX. He took the discrete logic design of the Cropredy Test Card Generator and put it into a CPLD programmable logic chip. He also found space for the PAL encoder. This gives a very compact design. My PCB for the design is only 2.6 by 1.8 inches. I've built the Mark2 version which was published in CQTV205.

Please take a look at Brian's website www.atv-projects.com for the background on this project and other ATV related projects.


Circuit Diagram

My circuit diagram is very similar to Brian's original circuit diagram. The main difference are the two oscillators. I have used "tiny logic" inverters to form an oscillator. My circuit includes a 7805 +5V regulator so the board can be run off a standard 12V supply.

QtyValue PackageParts
72k20603R1, R4, R11, R24, R25, R26, R27
21k0603R2, R5
13k90603R6
11k50603R7
61k20603R8, R14, R18, R23, R28, R30
18200603R9
16800603R10
24700603R12, R22
13k30603R13
210k0603R15, R16
1680603R20
1750603R21
215k0603R29, R31
139p0603C5
1330p0603C6
8100n0603C7, C10, C11, C13, C14, C15, C16, C17
1470u C9
11u C12
422p0603C18, C19, C20, C21
133u1812L1
117.73447MHzHC49/SXL1
116MHzHC49/SXL2
127C512APDIP28IC1
1M4A5-64/32PLCC44IC3
17805TO220IC4
21G04SOT23-5IC5, IC6
1BC848BC848T1
1BCX71BCX71SMDT2
2Header 2x1 JP1, JP2
1Header 5x1 JP3


Construction

The test card generator was built on double sided PCB. One side is plain copper and is used as the main ground. Through hole components are mounted on this side. All surface mount components are mounted on the track side of the PCB. The artwork should be printed out at 300dpi. The outer dimensions should be 2.6 by 1.8 inches, plus or minus a little bit. Placement diagrams for the top and bottom show where the components should be mounted.


Programming

When the unit is all built up it is time to program the CPLD. Using a small JTAG adapter connected to the parallel port and the Lattice download program it is a 5 second job. I built the JTAG adapter myself. You can find details on the web, I will put details of my version on this site when time allows. Then it's just a case of designing the testcards you want in the EPROM. Brian has a PC program to help develop the test cards. See his test card page for more info on this.

Acknowledgements

I would like to thank Brian for all the hard work and effort that has gone into this project. The picture on page 31 in CQTV202 shows his original test setup for the test card generator. It's a long way from the design he shows on his web site. Please take a look at his web site www.atv-projects.com.



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Just a quick disclaimer, if you fry something even if my design is wrong it is your problem! I have tried to make these details as accurate as possible but I accept no responsibility for any errors or omissions. There is no technical support for any of my projects.