Highspeed-Modem for the EPP

Jürgen Hasch, DG1SCR, Meisenstraße 23, 73066 Uhingen,

Motivation

Through the introduction of a 200kHz massive channel for Digital applications in the 70cm-Band, a growing demand emerges at Packet-Radio-components for throughputs clearly bigger than 9600 bps, mainly on the user-side.

Since short, Data-transceivers are with an accordingly big spread and a Tx/Rx switch-time <1ms available [1], however another certain narrow pass exists with the required modem-components. While a RMNC can serve exactly the channel on the Digi-side, the user is depended on relatively expensive solutions like TNC3 or USCC-slot-cards with additional modem.

A FSK-Modem, that can be connected at the interface of a PC and processes throughputs without bigger problems until over 100kBit, should be developed in order to manage remedy here.

The argument of the authors from [2] following, the parallel interface of the PC presents itself as inexpensive and almost everywhere existing connection-possibility at. With the EPP-Standard, also one is suitable for the modem-business, with a Datendurchsatzrate from> 500kB/s of the possible transfer-spread ago sufficient, interface existing. In the meantime PC-slot-cards are available with 2 or more EPP-Interfaces furthermore, so that older PCs can become dissarmed and also a possibly vohandener printers further can be driven. The price such addition-fixing is clearly settled under 50 DM.

The question that itself now puts is: How does such a modem leave itself as compact module and realize as favorably as possible to it?

A gaze into different subject journals, just as [3] and [4] shows a success-promising way: FPGAs!

What is a FPGA?

The abbreviation FPGA stands for „Field Programmable Gate Array“, translates roughly „in the application programmable accumulation of logic-gates“.

Such a component is a digitales module, i.e. with it only digitale circuits can be realized. Analogous Pedants to the FPGAs are however also known.

There is a row of manufacturers of such components, the two most renowned representatives are Xilinx and Altera. For the modem, one used a XC5204-Baustein of Xilinx, main-reason for it was [4], just as the lately introduced, for the amateur-purse affordable development-package of Xilinx. Other manufacturers offer in the meantime similar packages, with which the simple representatives of the respective component-series can be programmed, however.

One buys a FPGA of the manufacturer so, it is unprogrammed, i.e. it is components of the pole, that are only put in by the circuit-developer for a specific task. This is of course also an important point, that speaks in behalf of the use in an amateur-radio-project.

If one looks at the technologies to the programming of different FPGA-Families, so one can plan another division. Some families, the Cypress would example-point pASIC380, the Antifuse-Technologies use. The components are programmed with it in a particular programming-appliance, an additional alteration of the programming is possible no longer then.

Another technology puts the application of Flash-Speicherzellen, like which a Flash-Eproms, there. A particular programming-appliance or a programming-circuit is also necessary with it, however the programming can also be altered here again late.

SRAM-based FPGAs represent the third important variation. These must when aiming the care-tension from an external storage every time (for example a small EEPROM) again is programmed. For our application, this possibility offers many advantages. If one takes care of it, that the initialization of the FPGA can be planned from also the PC from, then an initialization is possible through the modem-driver of the PC. Consequently, driver-updates can become plan always matching to the current programming of the FPGA and improvements in the modem through simple Software-Update of the driver.

However now to the function-manner of a FPGA:

A FPGA contains a big number at basic logic-functions (logic-cells), that, as shown in illustration 1, together through logical channels can be connected:

DrawObject
Illustration 1: Structure of a FPGA

The programming of a FPGA means the manufacture of connections therefore once (Routing) between the single logic-cells.

A logic-cell itself usually consists of one or several logical reason-functions and a flip-flop. With her/it here started XC5200-Familie of Xilinx simply passes the gate-logic from a 16 bit of big storage-cell. For an any at the beginning of-combination at the four entrances, each wished Ausgangswert reprogrammed can become with it:


Illustration 2: Construction a logic-cell with the XC5200-Familie

Each logic-cell is programmable for itself separately. The selected component XC5204 of Xilinx contains 480 such logic-cells and reaches a Komplexizität of approximately 6000 gates with it.

Concept

With a Bitrate of approximately 100kBit/s, the modem should demand the PC an as low as possible cpu-peformance, since modern (Windows) Operating Systems already require a bulk of the cpu-performance.

In order to hold the Interrupt-Last of the PC's with reception low, a buffering of the reception-data is necessary, preferably should be decoded a complete Frame in the modem and is only released after verification of the CRC-checksum for the PC. Since would use with him/it XC5204-FPGA storage area is a valuable resource, an external 8k*8 RAM was intended to the storage.

The Sendefall is a little more simply based, here, the PC generates the transmit-data-stream including HDLC-Coding and Bitstuffung. Merely NRZI-Kodierung and Scrambler are component of the modem. Advantage this method is, that one can generate the required TX-Delay through putting in front of HDLC-Flags on the one hand and can nevertheless store the Sendedaten in the RAM of the modem.

The realization of the EPP-Interface is very simply solved. A data-access from the PC from reads or writes out a sign from the RAM of the modem and puts down a pointer on the next sign in the RAM simultaneously. With an Adresszugriff, the status-register is put down in the modem again, as well as finished reading.

The illustration shows the block-diagram of the modem:

DrawObject
Illustration 3: Function-blocks of the modem

The Entkopplung is property recognizable between the actual modem-part (RX and TX) and the EPP-Interface through the inter-storage of the data in the RAM.

The receiver (RX) exists from five Functional-blocks:

DrawObject
Illustration 4: Functional-blocks of the receiver

The clock-recovery and DCD-recognition happens in the DPLL. One supplies the 64th reception-clock to it and tries to regulate on the flanks of the data-signal. The DCD-recognition happens, in that is checked, whether an alteration of the reception-data occurs in the middle of the eye-opening. If this happens, the DCD is put back. In order to avoid a sticking of the DCD without signal, the DCD-recognition can be put back by the HDLC-Decoder, as soon as more than 7 consecutive Einsens were determined.

The HDLC-Decoder recognizes received HDLC-Flags and counts the number of that after a Flag received byte. Agree a Frame the figurative checksum with the calculated checksum in the end, the length of the received Frames is written before the Frame-Daten and is signalled the PC over a Interrupt that a Frame was received.

The station is very simply built:

DrawObject
Illustration 6: Function-blocks of the station

A new sign reads all RAM-controllers 8 bits from the external RAM. After NRZI-Kodierung and Scrambler, the data-stream is cared for a FIR-Filter to the Tiefpass-filterung. Outside the FPGA, the filter-exit is led on a D/A-Converter.

Hardware

In the appendix A is portrayed the diagram of the EPP-Modem. Central component the circuit is the FPGA, that is connected directly to the EPP-Schnittstelle of the PC, of course. If the modem-driver is started on the PC-side, so the FPGA is put back by means of Reset-Leitung and over the Write - and D0-Leitung of the printer-interface, the configuration-data are transferred into the FPGA in masses afterwards. After successful initialization, the FPGA reports, in that the Select-Leitung is put on +5V.

Since the FPGA possesses no own oscillator-circuit, is used a HA7210-Oszillatorbaustein of Harris as clock-sources with a 4,9152MHz quartz.

The Sendedatens coming from the internal FIR-Filter, that lie flat on the exits O0-O7, become over an as D/A-Converter beschaltetes resistance-network to an active low-passport-filter led and goes, after an impedance-transformer and a Trimmer to the level-attitude, on which output-plug.

The reception-signal coming from the radio equipment is first led on a impedance-transformer, followed from a low-passport-filter. A Komparator follows after it, that, ever after whether the received tension-value above or below the half business-tension lies, the data-stream to 1 or 0 adjudicates.

The PTT-Management is provided additionally with a Watchdog-Circuit, that should prevent, that a station goes on duration-program.

The complete circuit is looked after over a 5V tension-regulator. A business without own tension-care is not possible unfortunately, since all Ausgangspinses of the Printer-ports are used and whoever would already like that, as soon as zeros are transferred, the modem gets out?

Software

How already indicated, the preparation consists software of two parts, the programming of the FPGA and the letter of the modem-driver for the PC.

The FPGA-Programming happens to help of the software delivered by the manufacturer „Xilinx Foundation 1.4“, in a mixture between diagram-input and VHDL-Unterfunktionen.

The diagram-input is used for the most upper hierarchy-level of the circuit, in which all components must be wired only together. The graphic representation increases the clearness with it.

The actual modules in the modem are by means of the description-language „VHDL“ (Very High Speed Integrated Circuit High definition Language) realized. That is a Hardware-description-language, that, formulates kindly, also for digitale circuits in FPGA is been suitable. Opposite the diagram-input, the realization relieves itself here algorithmischer modules considerably, however about the price of an elevated resource-consumption and the low access on specific qualities of the chosen component-family.

On the PC-side, a Flexnet-Driver is in the development. The driver first enforces the configuration of the FPGA after program-start, in the business, it extends the packages decoded by the modem to Flexnet directly then through.

In the transmit-operation, the driver generates the raw-data required for the modem (i.e. it generates the HDLC-Flags, the Bitstuffing joins an and calculates the CRC-checksum). An any TX delay can through adds Flags from enough before the usefulness-data is reached.

Outlook

The development of the modem is not yet completed, since was not verified up to the press time of the receiver-part of the modem. Up to the lecture, hopefully newer realizations are vohanden here.

Through the possibility to Software-Updates, improvements are possible at the modem without big expenditure, so an improved transmission-part can simplify the PC's work for example. Another simple possibility must be found to it for the production of the wanted TX delay however.

Literature

  1. At Kurpiers DL8AAU and Martin Liebeck DL2ZBN: Hochgeschwindigkeits-Packet-Radio - a Transceiverkonzept for the 70cm tape
    Skriptum to the 13. International Packet-Radio convention

  2. W.-H. Rech DF9IC et al: A modem-adapter for the EPP
    Skriptum to the 13. International Packet-Radio Convention

  3. John Wiseman: Modern Digital Design for the Radio Amateur
    QEX Magazine, December 1997,

  4. Nico Palermo: Yet Another 9k6 Modem
    Description under http://www.microlet.com/yam

Appendix A: Diagram of the EPP-Modem

Diagram in the PDF-Format

Appendix B: Equipment-plan of the EPP-Modem

Equipment-plan in the GIF-Format