spectrumanalyzer.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000e80 00000000 00000000 00000094 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000000 00800060 00000e80 00000f14 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000096 00800060 00800060 00000f14 2**0 ALLOC 3 .noinit 00000000 008000f6 008000f6 00000f14 2**0 CONTENTS 4 .eeprom 00000000 00810000 00810000 00000f14 2**0 CONTENTS 5 .stab 00001de8 00000000 00000000 00000f14 2**2 CONTENTS, READONLY, DEBUGGING 6 .stabstr 000010c8 00000000 00000000 00002cfc 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 0c c0 rjmp .+24 ; 0x1a 2: 26 c0 rjmp .+76 ; 0x50 4: 25 c0 rjmp .+74 ; 0x50 6: 24 c0 rjmp .+72 ; 0x50 8: 23 c0 rjmp .+70 ; 0x50 a: 22 c0 rjmp .+68 ; 0x50 c: 21 c0 rjmp .+66 ; 0x50 e: 20 c0 rjmp .+64 ; 0x50 10: 1f c0 rjmp .+62 ; 0x50 12: b0 c4 rjmp .+2400 ; 0x974 14: 1d c0 rjmp .+58 ; 0x50 16: 6d c4 rjmp .+2266 ; 0x8f2 18: 1b c0 rjmp .+54 ; 0x50 0000001a <__ctors_end>: 1a: 11 24 eor r1, r1 1c: 1f be out 0x3f, r1 ; 63 1e: cf e5 ldi r28, 0x5F ; 95 20: d2 e0 ldi r29, 0x02 ; 2 22: de bf out 0x3e, r29 ; 62 24: cd bf out 0x3d, r28 ; 61 00000026 <__do_copy_data>: 26: 10 e0 ldi r17, 0x00 ; 0 28: a0 e6 ldi r26, 0x60 ; 96 2a: b0 e0 ldi r27, 0x00 ; 0 2c: e0 e8 ldi r30, 0x80 ; 128 2e: fe e0 ldi r31, 0x0E ; 14 30: 03 c0 rjmp .+6 ; 0x38 00000032 <.do_copy_data_loop>: 32: c8 95 lpm 34: 31 96 adiw r30, 0x01 ; 1 36: 0d 92 st X+, r0 00000038 <.do_copy_data_start>: 38: a0 36 cpi r26, 0x60 ; 96 3a: b1 07 cpc r27, r17 3c: d1 f7 brne .-12 ; 0x32 0000003e <__do_clear_bss>: 3e: 10 e0 ldi r17, 0x00 ; 0 40: a0 e6 ldi r26, 0x60 ; 96 42: b0 e0 ldi r27, 0x00 ; 0 44: 01 c0 rjmp .+2 ; 0x48 00000046 <.do_clear_bss_loop>: 46: 1d 92 st X+, r1 00000048 <.do_clear_bss_start>: 48: a6 3f cpi r26, 0xF6 ; 246 4a: b1 07 cpc r27, r17 4c: e1 f7 brne .-8 ; 0x46 4e: 47 c0 rjmp .+142 ; 0xde 00000050 <__bad_interrupt>: 50: d7 cf rjmp .-82 ; 0x0 00000052 : //! receives a string with the length len void uartReceiveStringLong(char *string, u08 len) { 52: cf 93 push r28 54: df 93 push r29 56: cd b7 in r28, 0x3d ; 61 58: de b7 in r29, 0x3e ; 62 5a: 25 97 sbiw r28, 0x05 ; 5 5c: 0f b6 in r0, 0x3f ; 63 5e: f8 94 cli 60: de bf out 0x3e, r29 ; 62 62: 0f be out 0x3f, r0 ; 63 64: cd bf out 0x3d, r28 ; 61 66: 89 83 std Y+1, r24 ; 0x01 68: 9a 83 std Y+2, r25 ; 0x02 6a: 6b 83 std Y+3, r22 ; 0x03 u08 i; u08 j; while (uartGetRxBuffer()->datalength: int main () { de: cb e3 ldi r28, 0x3B ; 59 e0: d2 e0 ldi r29, 0x02 ; 2 e2: de bf out 0x3e, r29 ; 62 e4: cd bf out 0x3d, r28 ; 61 enum {WAIT, GETOPT, SWEEP}; u08 status = WAIT; e6: 19 82 std Y+1, r1 ; 0x01 u08 input[12]; u32 freqStart=0; e8: 1e 86 std Y+14, r1 ; 0x0e ea: 1f 86 std Y+15, r1 ; 0x0f ec: 18 8a std Y+16, r1 ; 0x10 ee: 19 8a std Y+17, r1 ; 0x11 u32 freqStop=0; f0: 1a 8a std Y+18, r1 ; 0x12 f2: 1b 8a std Y+19, r1 ; 0x13 f4: 1c 8a std Y+20, r1 ; 0x14 f6: 1d 8a std Y+21, r1 ; 0x15 u32 freqStep=0; f8: 1e 8a std Y+22, r1 ; 0x16 fa: 1f 8a std Y+23, r1 ; 0x17 fc: 18 8e std Y+24, r1 ; 0x18 fe: 19 8e std Y+25, r1 ; 0x19 u32 freqCurrent = 0; 100: 1a 8e std Y+26, r1 ; 0x1a 102: 1b 8e std Y+27, r1 ; 0x1b 104: 1c 8e std Y+28, r1 ; 0x1c 106: 1d 8e std Y+29, r1 ; 0x1d u32 counter = 0; 108: 1e 8e std Y+30, r1 ; 0x1e 10a: 1f 8e std Y+31, r1 ; 0x1f 10c: 18 a2 std Y+32, r1 ; 0x20 10e: 19 a2 std Y+33, r1 ; 0x21 u08 firstsweep = FALSE; 110: 1a a2 std Y+34, r1 ; 0x22 ////// INITIALIZATION // enable and initialize the uart uartInit(); 112: 97 d2 rcall .+1326 ; 0x642 // set the uart baud rate uartSetBaudRate(115200); 114: 60 e0 ldi r22, 0x00 ; 0 116: 72 ec ldi r23, 0xC2 ; 194 118: 81 e0 ldi r24, 0x01 ; 1 11a: 90 e0 ldi r25, 0x00 ; 0 11c: e0 d2 rcall .+1472 ; 0x6de // initializes the SPI interface adc_init(); 11e: b5 d0 rcall .+362 ; 0x28a // initializes the DDS ports dds_init(); 120: 27 d1 rcall .+590 ; 0x370 // flush all data out of the receive buffer uartFlushReceiveBuffer(); 122: 94 d3 rcall .+1832 ; 0x84c ////// MAIN PROGRAM // endless loop while (1) { switch (status) 124: 89 81 ldd r24, Y+1 ; 0x01 126: 28 2f mov r18, r24 128: 33 27 eor r19, r19 12a: 2b a3 std Y+35, r18 ; 0x23 12c: 3c a3 std Y+36, r19 ; 0x24 12e: 8b a1 ldd r24, Y+35 ; 0x23 130: 9c a1 ldd r25, Y+36 ; 0x24 132: 81 30 cpi r24, 0x01 ; 1 134: 91 05 cpc r25, r1 136: b9 f0 breq .+46 ; 0x166 138: 2b a1 ldd r18, Y+35 ; 0x23 13a: 3c a1 ldd r19, Y+36 ; 0x24 13c: 22 30 cpi r18, 0x02 ; 2 13e: 31 05 cpc r19, r1 140: 2c f4 brge .+10 ; 0x14c 142: 8b a1 ldd r24, Y+35 ; 0x23 144: 9c a1 ldd r25, Y+36 ; 0x24 146: 00 97 sbiw r24, 0x00 ; 0 148: 39 f0 breq .+14 ; 0x158 14a: 9b c0 rjmp .+310 ; 0x282 14c: 2b a1 ldd r18, Y+35 ; 0x23 14e: 3c a1 ldd r19, Y+36 ; 0x24 150: 22 30 cpi r18, 0x02 ; 2 152: 31 05 cpc r19, r1 154: e9 f1 breq .+122 ; 0x1d0 156: 95 c0 rjmp .+298 ; 0x282 { ///////// // WAIT - Simply waits ... case WAIT: // If is a byte in the serial receive buffer, then // the status will be set to GETOPT because // the MCU have to wait for further options. if (uartReceiveBufferIsEmpty()==FALSE) 158: 84 d3 rcall .+1800 ; 0x862 15a: 88 23 and r24, r24 15c: 09 f0 breq .+2 ; 0x160 15e: 91 c0 rjmp .+290 ; 0x282 { status = GETOPT; 160: 81 e0 ldi r24, 0x01 ; 1 162: 89 83 std Y+1, r24 ; 0x01 } break; 164: 8e c0 rjmp .+284 ; 0x282 ///////// // GETOPT - Receives the options for one measurement cycle case GETOPT: // The MCU expects three unsigned longs // for start, stop and step delta phase values uartReceiveStringLong(input,12); 166: 8c 2f mov r24, r28 168: 9d 2f mov r25, r29 16a: 02 96 adiw r24, 0x02 ; 2 16c: 6c e0 ldi r22, 0x0C ; 12 16e: 71 df rcall .-286 ; 0x52 memcpy(&freqStart,input,sizeof(long)); 170: 8c 2f mov r24, r28 172: 9d 2f mov r25, r29 174: 02 96 adiw r24, 0x02 ; 2 176: 2c 2f mov r18, r28 178: 3d 2f mov r19, r29 17a: 22 5f subi r18, 0xF2 ; 242 17c: 3f 4f sbci r19, 0xFF ; 255 17e: 44 e0 ldi r20, 0x04 ; 4 180: 50 e0 ldi r21, 0x00 ; 0 182: 68 2f mov r22, r24 184: 79 2f mov r23, r25 186: 93 2f mov r25, r19 188: 82 2f mov r24, r18 18a: 17 d6 rcall .+3118 ; 0xdba memcpy(&freqStop,(input+4),sizeof(long)); 18c: 8c 2f mov r24, r28 18e: 9d 2f mov r25, r29 190: 02 96 adiw r24, 0x02 ; 2 192: 04 96 adiw r24, 0x04 ; 4 194: 2c 2f mov r18, r28 196: 3d 2f mov r19, r29 198: 2e 5e subi r18, 0xEE ; 238 19a: 3f 4f sbci r19, 0xFF ; 255 19c: 44 e0 ldi r20, 0x04 ; 4 19e: 50 e0 ldi r21, 0x00 ; 0 1a0: 68 2f mov r22, r24 1a2: 79 2f mov r23, r25 1a4: 93 2f mov r25, r19 1a6: 82 2f mov r24, r18 1a8: 08 d6 rcall .+3088 ; 0xdba memcpy(&freqStep,(input+8),sizeof(long)); 1aa: 8c 2f mov r24, r28 1ac: 9d 2f mov r25, r29 1ae: 02 96 adiw r24, 0x02 ; 2 1b0: 08 96 adiw r24, 0x08 ; 8 1b2: 2c 2f mov r18, r28 1b4: 3d 2f mov r19, r29 1b6: 2a 5e subi r18, 0xEA ; 234 1b8: 3f 4f sbci r19, 0xFF ; 255 1ba: 44 e0 ldi r20, 0x04 ; 4 1bc: 50 e0 ldi r21, 0x00 ; 0 1be: 68 2f mov r22, r24 1c0: 79 2f mov r23, r25 1c2: 93 2f mov r25, r19 1c4: 82 2f mov r24, r18 1c6: f9 d5 rcall .+3058 ; 0xdba // Clear the receive buffer uartFlushReceiveBuffer(); 1c8: 41 d3 rcall .+1666 ; 0x84c // Sets the status to SWEEP status = SWEEP; 1ca: 82 e0 ldi r24, 0x02 ; 2 1cc: 89 83 std Y+1, r24 ; 0x01 break; 1ce: 59 c0 rjmp .+178 ; 0x282 ///////// // SWEEP - Measures the power spectrum density for the preset // frequency range case SWEEP: // Puts the DDS in well defined state dds_reset(); 1d0: e4 d0 rcall .+456 ; 0x39a // Does measure until the current frequency has // reached the stop frequency firstsweep = TRUE; 1d2: 8f ef ldi r24, 0xFF ; 255 1d4: 8a a3 std Y+34, r24 ; 0x22 counter=0; 1d6: 1e 8e std Y+30, r1 ; 0x1e 1d8: 1f 8e std Y+31, r1 ; 0x1f 1da: 18 a2 std Y+32, r1 ; 0x20 1dc: 19 a2 std Y+33, r1 ; 0x21 while ((freqCurrent < (freqStop-freqStep)) ) 1de: 2a 89 ldd r18, Y+18 ; 0x12 1e0: 3b 89 ldd r19, Y+19 ; 0x13 1e2: 4c 89 ldd r20, Y+20 ; 0x14 1e4: 5d 89 ldd r21, Y+21 ; 0x15 1e6: 8e 89 ldd r24, Y+22 ; 0x16 1e8: 9f 89 ldd r25, Y+23 ; 0x17 1ea: a8 8d ldd r26, Y+24 ; 0x18 1ec: b9 8d ldd r27, Y+25 ; 0x19 1ee: 28 1b sub r18, r24 1f0: 39 0b sbc r19, r25 1f2: 4a 0b sbc r20, r26 1f4: 5b 0b sbc r21, r27 1f6: 8a 8d ldd r24, Y+26 ; 0x1a 1f8: 9b 8d ldd r25, Y+27 ; 0x1b 1fa: ac 8d ldd r26, Y+28 ; 0x1c 1fc: bd 8d ldd r27, Y+29 ; 0x1d 1fe: 82 17 cp r24, r18 200: 93 07 cpc r25, r19 202: a4 07 cpc r26, r20 204: b5 07 cpc r27, r21 206: 08 f0 brcs .+2 ; 0x20a 208: 3b c0 rjmp .+118 ; 0x280 { // Computes the current center frequency with the // discrete frequency step and the counter freqCurrent=(u32)freqStart + (u32)counter * (u32)freqStep; 20a: 2e 89 ldd r18, Y+22 ; 0x16 20c: 3f 89 ldd r19, Y+23 ; 0x17 20e: 48 8d ldd r20, Y+24 ; 0x18 210: 59 8d ldd r21, Y+25 ; 0x19 212: 6e 8d ldd r22, Y+30 ; 0x1e 214: 7f 8d ldd r23, Y+31 ; 0x1f 216: 88 a1 ldd r24, Y+32 ; 0x20 218: 99 a1 ldd r25, Y+33 ; 0x21 21a: da d5 rcall .+2996 ; 0xdd0 21c: 26 2f mov r18, r22 21e: 37 2f mov r19, r23 220: 48 2f mov r20, r24 222: 59 2f mov r21, r25 224: 8e 85 ldd r24, Y+14 ; 0x0e 226: 9f 85 ldd r25, Y+15 ; 0x0f 228: a8 89 ldd r26, Y+16 ; 0x10 22a: b9 89 ldd r27, Y+17 ; 0x11 22c: 82 0f add r24, r18 22e: 93 1f adc r25, r19 230: a4 1f adc r26, r20 232: b5 1f adc r27, r21 234: 8a 8f std Y+26, r24 ; 0x1a 236: 9b 8f std Y+27, r25 ; 0x1b 238: ac 8f std Y+28, r26 ; 0x1c 23a: bd 8f std Y+29, r27 ; 0x1d counter++; 23c: 8e 8d ldd r24, Y+30 ; 0x1e 23e: 9f 8d ldd r25, Y+31 ; 0x1f 240: a8 a1 ldd r26, Y+32 ; 0x20 242: b9 a1 ldd r27, Y+33 ; 0x21 244: 01 96 adiw r24, 0x01 ; 1 246: a1 1d adc r26, r1 248: b1 1d adc r27, r1 24a: 8e 8f std Y+30, r24 ; 0x1e 24c: 9f 8f std Y+31, r25 ; 0x1f 24e: a8 a3 std Y+32, r26 ; 0x20 250: b9 a3 std Y+33, r27 ; 0x21 // Sets the variable frequency oscillator (VFO) // to the current frequency dds_setfrequency(freqCurrent); 252: 6a 8d ldd r22, Y+26 ; 0x1a 254: 7b 8d ldd r23, Y+27 ; 0x1b 256: 8c 8d ldd r24, Y+28 ; 0x1c 258: 9d 8d ldd r25, Y+29 ; 0x1d 25a: 52 d1 rcall .+676 ; 0x500 // After wait, the measured section was tuned. if (firstsweep==FALSE) { 25c: 8a a1 ldd r24, Y+34 ; 0x22 25e: 88 23 and r24, r24 260: 31 f4 brne .+12 ; 0x26e delay_ms(2); 262: 68 e9 ldi r22, 0x98 ; 152 264: 79 e0 ldi r23, 0x09 ; 9 266: 80 e0 ldi r24, 0x00 ; 0 268: 90 e0 ldi r25, 0x00 ; 0 26a: c6 d1 rcall .+908 ; 0x5f8 26c: 06 c0 rjmp .+12 ; 0x27a } else { delay_ms(20); 26e: 60 ef ldi r22, 0xF0 ; 240 270: 7f e5 ldi r23, 0x5F ; 95 272: 80 e0 ldi r24, 0x00 ; 0 274: 90 e0 ldi r25, 0x00 ; 0 276: c0 d1 rcall .+896 ; 0x5f8 firstsweep=FALSE; 278: 1a a2 std Y+34, r1 ; 0x22 } // Sends the value from the ADC to the PC uartSendByte(adc_read_channel_one()); 27a: 14 d0 rcall .+40 ; 0x2a4 27c: 97 d2 rcall .+1326 ; 0x7ac 27e: af cf rjmp .-162 ; 0x1de } // After one measurement cycle the status is set // to WAIT status = WAIT; 280: 19 82 std Y+1, r1 ; 0x01 break; } // The delay is intended for interrupt driven uart. delay_us(20); 282: 84 e2 ldi r24, 0x24 ; 36 284: 90 e0 ldi r25, 0x00 ; 0 286: 9c d1 rcall .+824 ; 0x5c0 288: 4d cf rjmp .-358 ; 0x124 0000028a : ////// FUNCTIONS // Initializes the SPI interface void adc_init(void) { 28a: cf 93 push r28 28c: df 93 push r29 28e: cd b7 in r28, 0x3d ; 61 290: de b7 in r29, 0x3e ; 62 // Set the following pins as output DDRB = _BV(SPI_SS) | _BV(SPI_SCK) | _BV(SPI_MOSI); 292: 80 eb ldi r24, 0xB0 ; 176 294: 80 93 37 00 sts 0x0037, r24 // Set the PORTB up to the SPI modus and set the microcontroller as master SPCR = _BV(SPE) | _BV(MSTR); 298: 80 e5 ldi r24, 0x50 ; 80 29a: 80 93 2d 00 sts 0x002D, r24 } 29e: df 91 pop r29 2a0: cf 91 pop r28 2a2: 08 95 ret 000002a4 : // Start the analog-to-digital conversion for channel 1 // and returns an unsigned char value. u08 adc_read_channel_one(void) { 2a4: cf 93 push r28 2a6: df 93 push r29 2a8: cd b7 in r28, 0x3d ; 61 2aa: de b7 in r29, 0x3e ; 62 2ac: 21 97 sbiw r28, 0x01 ; 1 2ae: 0f b6 in r0, 0x3f ; 63 2b0: f8 94 cli 2b2: de bf out 0x3e, r29 ; 62 2b4: 0f be out 0x3f, r0 ; 63 2b6: cd bf out 0x3d, r28 ; 61 u08 retval; // No interrupts due to critical timing operations cli(); 2b8: f8 94 cli // Selects channel one by setting CNVST to HIGH and LOW once // max1118 datasheet: t_csh_min = 100 ns = 0.1 µs PORTB |= _BV(ADC_CNVST); 2ba: 80 91 38 00 lds r24, 0x0038 2be: 88 60 ori r24, 0x08 ; 8 2c0: 80 93 38 00 sts 0x0038, r24 delay_char(1); // 678 ns with 7.3728 MHz 2c4: 81 e0 ldi r24, 0x01 ; 1 2c6: 63 d1 rcall .+710 ; 0x58e PORTB &= ~_BV(ADC_CNVST); 2c8: 80 91 38 00 lds r24, 0x0038 2cc: 87 7f andi r24, 0xF7 ; 247 2ce: 80 93 38 00 sts 0x0038, r24 // Waiting for analog-to-digital conversion for the time t_conv_max=7,5 µs delay_us(8); 2d2: 8e e0 ldi r24, 0x0E ; 14 2d4: 90 e0 ldi r25, 0x00 ; 0 2d6: 74 d1 rcall .+744 ; 0x5c0 // SPI is a synchron serial peripheral interface so the data are // transmitted over the MISO and MOSI wire at the same time. // An output operation at the MOSI wire starts the whole // transmission cycle and activates the synchron clock signal // at the SCK wire. After the cycle the byte which was transmitted // from the slave is in the SPDR shift register. SPDR=0xFF; 2d8: 8f ef ldi r24, 0xFF ; 255 2da: 80 93 2f 00 sts 0x002F, r24 // Returns the MISO value from the shift register SPDR retval = SPDR; 2de: 80 91 2f 00 lds r24, 0x002F 2e2: 89 83 std Y+1, r24 ; 0x01 // Critical timing is over so interrupts are allowed. sei(); 2e4: 78 94 sei return retval; 2e6: 89 81 ldd r24, Y+1 ; 0x01 2e8: 99 27 eor r25, r25 } 2ea: 21 96 adiw r28, 0x01 ; 1 2ec: 0f b6 in r0, 0x3f ; 63 2ee: f8 94 cli 2f0: de bf out 0x3e, r29 ; 62 2f2: 0f be out 0x3f, r0 ; 63 2f4: cd bf out 0x3d, r28 ; 61 2f6: df 91 pop r29 2f8: cf 91 pop r28 2fa: 08 95 ret 000002fc : // Start the analog-to-digital conversion for channel 2 // and returns an unsigned char value. u08 adc_read_channel_two(void) { 2fc: cf 93 push r28 2fe: df 93 push r29 300: cd b7 in r28, 0x3d ; 61 302: de b7 in r29, 0x3e ; 62 304: 21 97 sbiw r28, 0x01 ; 1 306: 0f b6 in r0, 0x3f ; 63 308: f8 94 cli 30a: de bf out 0x3e, r29 ; 62 30c: 0f be out 0x3f, r0 ; 63 30e: cd bf out 0x3d, r28 ; 61 u08 retval; // No interrupts due to critical timing operations cli(); 310: f8 94 cli // Selects channel two by setting CNVST to HIGH and LOW twice PORTB |= _BV(ADC_CNVST); 312: 80 91 38 00 lds r24, 0x0038 316: 88 60 ori r24, 0x08 ; 8 318: 80 93 38 00 sts 0x0038, r24 delay_char(1); 31c: 81 e0 ldi r24, 0x01 ; 1 31e: 37 d1 rcall .+622 ; 0x58e PORTB &= ~_BV(ADC_CNVST); 320: 80 91 38 00 lds r24, 0x0038 324: 87 7f andi r24, 0xF7 ; 247 326: 80 93 38 00 sts 0x0038, r24 delay_char(1); 32a: 81 e0 ldi r24, 0x01 ; 1 32c: 30 d1 rcall .+608 ; 0x58e PORTB |= _BV(ADC_CNVST); 32e: 80 91 38 00 lds r24, 0x0038 332: 88 60 ori r24, 0x08 ; 8 334: 80 93 38 00 sts 0x0038, r24 delay_char(1); 338: 81 e0 ldi r24, 0x01 ; 1 33a: 29 d1 rcall .+594 ; 0x58e PORTB &= ~_BV(ADC_CNVST); 33c: 80 91 38 00 lds r24, 0x0038 340: 87 7f andi r24, 0xF7 ; 247 342: 80 93 38 00 sts 0x0038, r24 // Waiting for analog-to-digital conversion for the time t_conv_max=7,5 µs delay_us(8); 346: 8e e0 ldi r24, 0x0E ; 14 348: 90 e0 ldi r25, 0x00 ; 0 34a: 3a d1 rcall .+628 ; 0x5c0 // SPI is a synchron serial peripheral interface so the data are // transmitted over the MISO and MOSI wire at the same time. // An output operation at the MOSI wire starts the whole // transmission cycle and activates the synchron clock signal // at the SCK wire. After the cycle the byte which was transmitted // from the slave is in the SPDR shift register. SPDR=0xFF; // 0x18 == 00011000 34c: 8f ef ldi r24, 0xFF ; 255 34e: 80 93 2f 00 sts 0x002F, r24 // Returns the MISO value from the shift register SPDR retval = SPDR; 352: 80 91 2f 00 lds r24, 0x002F 356: 89 83 std Y+1, r24 ; 0x01 // Critical timing is over so interrupts are allowed. sei(); 358: 78 94 sei return retval; 35a: 89 81 ldd r24, Y+1 ; 0x01 35c: 99 27 eor r25, r25 } 35e: 21 96 adiw r28, 0x01 ; 1 360: 0f b6 in r0, 0x3f ; 63 362: f8 94 cli 364: de bf out 0x3e, r29 ; 62 366: 0f be out 0x3f, r0 ; 63 368: cd bf out 0x3d, r28 ; 61 36a: df 91 pop r29 36c: cf 91 pop r28 36e: 08 95 ret 00000370 : #define SET_SERIAL_MODE 3 void dds_init(void) { 370: cf 93 push r28 372: df 93 push r29 374: cd b7 in r28, 0x3d ; 61 376: de b7 in r29, 0x3e ; 62 // Set pins 4, 5 and 7 of PORTA to output DDRA = _BV(DDS_DATALOAD) | _BV(DDS_SETFREQ) | _BV(DDS_RESET); 378: 80 eb ldi r24, 0xB0 ; 176 37a: 80 93 3a 00 sts 0x003A, r24 PORTA = 0x00; 37e: 10 92 3b 00 sts 0x003B, r1 // Sets the whole PORTC to output DDRC = 0xFF; 382: 8f ef ldi r24, 0xFF ; 255 384: 80 93 34 00 sts 0x0034, r24 PORTC = 0x00; 388: 10 92 35 00 sts 0x0035, r1 delay_us(1); 38c: 81 e0 ldi r24, 0x01 ; 1 38e: 90 e0 ldi r25, 0x00 ; 0 390: 17 d1 rcall .+558 ; 0x5c0 dds_reset(); 392: 03 d0 rcall .+6 ; 0x39a } 394: df 91 pop r29 396: cf 91 pop r28 398: 08 95 ret 0000039a : void dds_reset(void) { 39a: cf 93 push r28 39c: df 93 push r29 39e: cd b7 in r28, 0x3d ; 61 3a0: de b7 in r29, 0x3e ; 62 cli(); 3a2: f8 94 cli // DDS_RESET to 1 PORTA |= _BV(DDS_RESET); 3a4: 80 91 3b 00 lds r24, 0x003B 3a8: 80 68 ori r24, 0x80 ; 128 3aa: 80 93 3b 00 sts 0x003B, r24 // datasheet: wait 5 SYSCLK + 7 ns == 91 ns with 60 MHz SYSCLK delay_us(1); 3ae: 81 e0 ldi r24, 0x01 ; 1 3b0: 90 e0 ldi r25, 0x00 ; 0 3b2: 06 d1 rcall .+524 ; 0x5c0 // DDS_RESET to 0 PORTA &= ~_BV(DDS_RESET); 3b4: 9f e7 ldi r25, 0x7F ; 127 3b6: 80 91 3b 00 lds r24, 0x003B 3ba: 89 23 and r24, r25 3bc: 80 93 3b 00 sts 0x003B, r24 // datasheet: wait 8 SYSCLK == 134 ns with 60 MHz SYSCLK delay_us(1); 3c0: 81 e0 ldi r24, 0x01 ; 1 3c2: 90 e0 ldi r25, 0x00 ; 0 3c4: fd d0 rcall .+506 ; 0x5c0 sei(); 3c6: 78 94 sei } 3c8: df 91 pop r29 3ca: cf 91 pop r28 3cc: 08 95 ret 000003ce : void dds_write_serial(u08 data[5]) { 3ce: cf 93 push r28 3d0: df 93 push r29 3d2: cd b7 in r28, 0x3d ; 61 3d4: de b7 in r29, 0x3e ; 62 3d6: 27 97 sbiw r28, 0x07 ; 7 3d8: 0f b6 in r0, 0x3f ; 63 3da: f8 94 cli 3dc: de bf out 0x3e, r29 ; 62 3de: 0f be out 0x3f, r0 ; 63 3e0: cd bf out 0x3d, r28 ; 61 3e2: 89 83 std Y+1, r24 ; 0x01 3e4: 9a 83 std Y+2, r25 ; 0x02 int i,j; u08 tmp; cli(); 3e6: f8 94 cli // Sets the DDS into the serial mode / source: AD8951 data sheet PORTC = 3; 3e8: 83 e0 ldi r24, 0x03 ; 3 3ea: 80 93 35 00 sts 0x0035, r24 // DDS_DATALOAD to 1 PORTA |= _BV(DDS_DATALOAD); 3ee: 80 91 3b 00 lds r24, 0x003B 3f2: 80 61 ori r24, 0x10 ; 16 3f4: 80 93 3b 00 sts 0x003B, r24 delay_nop(); // 136 ns with 7.3728 MHz // datasheet: 3.5ns 3f8: c2 d0 rcall .+388 ; 0x57e // DDS_DATALOAD to 0 PORTA &= ~_BV(DDS_DATALOAD); 3fa: 80 91 3b 00 lds r24, 0x003B 3fe: 8f 7e andi r24, 0xEF ; 239 400: 80 93 3b 00 sts 0x003B, r24 delay_us(1); 404: 81 e0 ldi r24, 0x01 ; 1 406: 90 e0 ldi r25, 0x00 ; 0 408: db d0 rcall .+438 ; 0x5c0 // DDS_SETFREQ to 1 PORTA |= _BV(DDS_SETFREQ); 40a: 80 91 3b 00 lds r24, 0x003B 40e: 80 62 ori r24, 0x20 ; 32 410: 80 93 3b 00 sts 0x003B, r24 delay_nop(); // 136 ns with 7.3728 MHz // datasheet: 7ns 414: b4 d0 rcall .+360 ; 0x57e // DDS_SETFREQ to 0 PORTA &= ~_BV(DDS_SETFREQ); 416: 80 91 3b 00 lds r24, 0x003B 41a: 8f 7d andi r24, 0xDF ; 223 41c: 80 93 3b 00 sts 0x003B, r24 delay_us(1); 420: 81 e0 ldi r24, 0x01 ; 1 422: 90 e0 ldi r25, 0x00 ; 0 424: cd d0 rcall .+410 ; 0x5c0 // data[4] is byte #1 (status bits and 6xREFCLK on) // data[3] is byte #2 (first byte) // data[0] is byte #5 (last byte) for (i=0;i<5;i++) 426: 1b 82 std Y+3, r1 ; 0x03 428: 1c 82 std Y+4, r1 ; 0x04 42a: 8b 81 ldd r24, Y+3 ; 0x03 42c: 9c 81 ldd r25, Y+4 ; 0x04 42e: 85 30 cpi r24, 0x05 ; 5 430: 91 05 cpc r25, r1 432: 0c f0 brlt .+2 ; 0x436 434: 4b c0 rjmp .+150 ; 0x4cc { tmp=data[i]; 436: 29 81 ldd r18, Y+1 ; 0x01 438: 3a 81 ldd r19, Y+2 ; 0x02 43a: 8b 81 ldd r24, Y+3 ; 0x03 43c: 9c 81 ldd r25, Y+4 ; 0x04 43e: f3 2f mov r31, r19 440: e2 2f mov r30, r18 442: e8 0f add r30, r24 444: f9 1f adc r31, r25 446: 80 81 ld r24, Z 448: 8f 83 std Y+7, r24 ; 0x07 for (j=0; j<8; j++) 44a: 1d 82 std Y+5, r1 ; 0x05 44c: 1e 82 std Y+6, r1 ; 0x06 44e: 8d 81 ldd r24, Y+5 ; 0x05 450: 9e 81 ldd r25, Y+6 ; 0x06 452: 88 30 cpi r24, 0x08 ; 8 454: 91 05 cpc r25, r1 456: 0c f0 brlt .+2 ; 0x45a 458: 32 c0 rjmp .+100 ; 0x4be { // Sends only the MSB (D7) to the DDS in serial mode PORTC = (tmp & _BV(j)) << (7-j); 45a: 8f 81 ldd r24, Y+7 ; 0x07 45c: 28 2f mov r18, r24 45e: 33 27 eor r19, r19 460: 81 e0 ldi r24, 0x01 ; 1 462: 90 e0 ldi r25, 0x00 ; 0 464: 0d 80 ldd r0, Y+5 ; 0x05 466: 02 c0 rjmp .+4 ; 0x46c 468: 88 0f add r24, r24 46a: 99 1f adc r25, r25 46c: 0a 94 dec r0 46e: e2 f7 brpl .-8 ; 0x468 470: 53 2f mov r21, r19 472: 42 2f mov r20, r18 474: 48 23 and r20, r24 476: 59 23 and r21, r25 478: 27 e0 ldi r18, 0x07 ; 7 47a: 30 e0 ldi r19, 0x00 ; 0 47c: 8d 81 ldd r24, Y+5 ; 0x05 47e: 9e 81 ldd r25, Y+6 ; 0x06 480: 28 1b sub r18, r24 482: 39 0b sbc r19, r25 484: 93 2f mov r25, r19 486: 82 2f mov r24, r18 488: 02 c0 rjmp .+4 ; 0x48e 48a: 44 0f add r20, r20 48c: 55 1f adc r21, r21 48e: 8a 95 dec r24 490: e2 f7 brpl .-8 ; 0x48a 492: 95 2f mov r25, r21 494: 84 2f mov r24, r20 496: 80 93 35 00 sts 0x0035, r24 delay_nop(); // 136 ns with 7.3728 MHz 49a: 71 d0 rcall .+226 ; 0x57e PORTA |= _BV(DDS_DATALOAD); // DDS_DATALOAD AUF 1 49c: 80 91 3b 00 lds r24, 0x003B 4a0: 80 61 ori r24, 0x10 ; 16 4a2: 80 93 3b 00 sts 0x003B, r24 delay_nop(); // 136 ns with 7.3728 MHz 4a6: 6b d0 rcall .+214 ; 0x57e PORTA &= ~_BV(DDS_DATALOAD); // DDS_DATALOAD AUF 0 4a8: 80 91 3b 00 lds r24, 0x003B 4ac: 8f 7e andi r24, 0xEF ; 239 4ae: 80 93 3b 00 sts 0x003B, r24 4b2: 8d 81 ldd r24, Y+5 ; 0x05 4b4: 9e 81 ldd r25, Y+6 ; 0x06 4b6: 01 96 adiw r24, 0x01 ; 1 4b8: 8d 83 std Y+5, r24 ; 0x05 4ba: 9e 83 std Y+6, r25 ; 0x06 4bc: c8 cf rjmp .-112 ; 0x44e } delay_nop(); 4be: 5f d0 rcall .+190 ; 0x57e 4c0: 8b 81 ldd r24, Y+3 ; 0x03 4c2: 9c 81 ldd r25, Y+4 ; 0x04 4c4: 01 96 adiw r24, 0x01 ; 1 4c6: 8b 83 std Y+3, r24 ; 0x03 4c8: 9c 83 std Y+4, r25 ; 0x04 4ca: af cf rjmp .-162 ; 0x42a } PORTC=0x00; 4cc: 10 92 35 00 sts 0x0035, r1 // DDS_SETFREQ to 1 PORTA |= _BV(DDS_SETFREQ); 4d0: 80 91 3b 00 lds r24, 0x003B 4d4: 80 62 ori r24, 0x20 ; 32 4d6: 80 93 3b 00 sts 0x003B, r24 delay_nop(); // 136 ns with 7.3728 MHz // datasheet: 7ns 4da: 51 d0 rcall .+162 ; 0x57e // DDS_SETFREQ to 0 PORTA &= ~_BV(DDS_SETFREQ); 4dc: 80 91 3b 00 lds r24, 0x003B 4e0: 8f 7d andi r24, 0xDF ; 223 4e2: 80 93 3b 00 sts 0x003B, r24 delay_us(1); // wait 1µs 4e6: 81 e0 ldi r24, 0x01 ; 1 4e8: 90 e0 ldi r25, 0x00 ; 0 4ea: 6a d0 rcall .+212 ; 0x5c0 // datasheet: wait 18clk - 7ns wih 60 MHZ: 300 ns - 7 ns == 293 ns sei(); 4ec: 78 94 sei } 4ee: 27 96 adiw r28, 0x07 ; 7 4f0: 0f b6 in r0, 0x3f ; 63 4f2: f8 94 cli 4f4: de bf out 0x3e, r29 ; 62 4f6: 0f be out 0x3f, r0 ; 63 4f8: cd bf out 0x3d, r28 ; 61 4fa: df 91 pop r29 4fc: cf 91 pop r28 4fe: 08 95 ret 00000500 : void dds_setfrequency(u32 deltaphase) { 500: cf 93 push r28 502: df 93 push r29 504: cd b7 in r28, 0x3d ; 61 506: de b7 in r29, 0x3e ; 62 508: 2c 97 sbiw r28, 0x0c ; 12 50a: 0f b6 in r0, 0x3f ; 63 50c: f8 94 cli 50e: de bf out 0x3e, r29 ; 62 510: 0f be out 0x3f, r0 ; 63 512: cd bf out 0x3d, r28 ; 61 514: 69 83 std Y+1, r22 ; 0x01 516: 7a 83 std Y+2, r23 ; 0x02 518: 8b 83 std Y+3, r24 ; 0x03 51a: 9c 83 std Y+4, r25 ; 0x04 u08 data[5]; u08 i; u08 *p_char; // Initialize frequency data array // 6xREFCLK is active data[4]=1; 51c: 81 e0 ldi r24, 0x01 ; 1 51e: 89 87 std Y+9, r24 ; 0x09 // p_char points to the last byte of the long-variable freq p_char = &deltaphase; 520: 8c 2f mov r24, r28 522: 9d 2f mov r25, r29 524: 01 96 adiw r24, 0x01 ; 1 526: 8b 87 std Y+11, r24 ; 0x0b 528: 9c 87 std Y+12, r25 ; 0x0c for (i=0;i<4;i++){ 52a: 1a 86 std Y+10, r1 ; 0x0a 52c: 8a 85 ldd r24, Y+10 ; 0x0a 52e: 84 30 cpi r24, 0x04 ; 4 530: 08 f0 brcs .+2 ; 0x534 532: 18 c0 rjmp .+48 ; 0x564 data[i]=*p_char; 534: 8a 85 ldd r24, Y+10 ; 0x0a 536: 28 2f mov r18, r24 538: 33 27 eor r19, r19 53a: 8c 2f mov r24, r28 53c: 9d 2f mov r25, r29 53e: 01 96 adiw r24, 0x01 ; 1 540: 82 0f add r24, r18 542: 93 1f adc r25, r19 544: b9 2f mov r27, r25 546: a8 2f mov r26, r24 548: 14 96 adiw r26, 0x04 ; 4 54a: eb 85 ldd r30, Y+11 ; 0x0b 54c: fc 85 ldd r31, Y+12 ; 0x0c 54e: 80 81 ld r24, Z 550: 8c 93 st X, r24 p_char++; 552: 8b 85 ldd r24, Y+11 ; 0x0b 554: 9c 85 ldd r25, Y+12 ; 0x0c 556: 01 96 adiw r24, 0x01 ; 1 558: 8b 87 std Y+11, r24 ; 0x0b 55a: 9c 87 std Y+12, r25 ; 0x0c 55c: 8a 85 ldd r24, Y+10 ; 0x0a 55e: 8f 5f subi r24, 0xFF ; 255 560: 8a 87 std Y+10, r24 ; 0x0a 562: e4 cf rjmp .-56 ; 0x52c } dds_write_serial(data); 564: 8c 2f mov r24, r28 566: 9d 2f mov r25, r29 568: 05 96 adiw r24, 0x05 ; 5 56a: 31 df rcall .-414 ; 0x3ce } 56c: 2c 96 adiw r28, 0x0c ; 12 56e: 0f b6 in r0, 0x3f ; 63 570: f8 94 cli 572: de bf out 0x3e, r29 ; 62 574: 0f be out 0x3f, r0 ; 63 576: cd bf out 0x3d, r28 ; 61 578: df 91 pop r29 57a: cf 91 pop r28 57c: 08 95 ret 0000057e : #if USE_DELAY_FUNCTIONS == 1 void delay_nop(void) { 57e: cf 93 push r28 580: df 93 push r29 582: cd b7 in r28, 0x3d ; 61 584: de b7 in r29, 0x3e ; 62 __asm__ volatile ( "nop\n\t" : : ); 586: 00 00 nop } 588: df 91 pop r29 58a: cf 91 pop r28 58c: 08 95 ret 0000058e : void delay_char(unsigned char number_of_loops) { 58e: cf 93 push r28 590: df 93 push r29 592: cd b7 in r28, 0x3d ; 61 594: de b7 in r29, 0x3e ; 62 596: 21 97 sbiw r28, 0x01 ; 1 598: 0f b6 in r0, 0x3f ; 63 59a: f8 94 cli 59c: de bf out 0x3e, r29 ; 62 59e: 0f be out 0x3f, r0 ; 63 5a0: cd bf out 0x3d, r28 ; 61 5a2: 89 83 std Y+1, r24 ; 0x01 /* 3 cpu cycles per loop + 10 cycles overhead when a constant is passed. */ __asm__ volatile ( "cp %A0,__zero_reg__ \n\t" \ 5a4: 89 81 ldd r24, Y+1 ; 0x01 5a6: 81 15 cp r24, r1 5a8: 11 f0 breq .+4 ; 0x5ae 000005aa : 5aa: 8a 95 dec r24 5ac: f1 f7 brne .-4 ; 0x5aa 000005ae : "breq L_EXIT_%= \n\t" \ "L_%=: \n\t" \ "dec %A0 \n\t" \ "brne L_%= \n\t" \ "L_EXIT_%=: \n\t" \ : /* NO OUTPUT */ \ : "r" (number_of_loops) \ ); return; } 5ae: 21 96 adiw r28, 0x01 ; 1 5b0: 0f b6 in r0, 0x3f ; 63 5b2: f8 94 cli 5b4: de bf out 0x3e, r29 ; 62 5b6: 0f be out 0x3f, r0 ; 63 5b8: cd bf out 0x3d, r28 ; 61 5ba: df 91 pop r29 5bc: cf 91 pop r28 5be: 08 95 ret 000005c0 : void delay_short(unsigned short number_of_loops) { 5c0: cf 93 push r28 5c2: df 93 push r29 5c4: cd b7 in r28, 0x3d ; 61 5c6: de b7 in r29, 0x3e ; 62 5c8: 22 97 sbiw r28, 0x02 ; 2 5ca: 0f b6 in r0, 0x3f ; 63 5cc: f8 94 cli 5ce: de bf out 0x3e, r29 ; 62 5d0: 0f be out 0x3f, r0 ; 63 5d2: cd bf out 0x3d, r28 ; 61 5d4: 89 83 std Y+1, r24 ; 0x01 5d6: 9a 83 std Y+2, r25 ; 0x02 /* 4 cpu cycles per loop + 12 cycles overhead when a constant is passed. */ __asm__ volatile ( "cp %A0,__zero_reg__ \n\t" \ 5d8: 89 81 ldd r24, Y+1 ; 0x01 5da: 9a 81 ldd r25, Y+2 ; 0x02 5dc: 81 15 cp r24, r1 5de: 91 05 cpc r25, r1 5e0: 11 f0 breq .+4 ; 0x5e6 000005e2 : 5e2: 01 97 sbiw r24, 0x01 ; 1 5e4: f1 f7 brne .-4 ; 0x5e2 000005e6 : "cpc %B0,__zero_reg__ \n\t" \ "breq L_EXIT_%= \n\t" \ "L_%=: \n\t" \ "sbiw r24,1 \n\t" \ "brne L_%= \n\t" \ "L_EXIT_%=: \n\t" \ : /* NO OUTPUT */ \ : "w" (number_of_loops) \ ); return; } 5e6: 22 96 adiw r28, 0x02 ; 2 5e8: 0f b6 in r0, 0x3f ; 63 5ea: f8 94 cli 5ec: de bf out 0x3e, r29 ; 62 5ee: 0f be out 0x3f, r0 ; 63 5f0: cd bf out 0x3d, r28 ; 61 5f2: df 91 pop r29 5f4: cf 91 pop r28 5f6: 08 95 ret 000005f8 : void delay_long(unsigned long number_of_loops) { 5f8: cf 93 push r28 5fa: df 93 push r29 5fc: cd b7 in r28, 0x3d ; 61 5fe: de b7 in r29, 0x3e ; 62 600: 24 97 sbiw r28, 0x04 ; 4 602: 0f b6 in r0, 0x3f ; 63 604: f8 94 cli 606: de bf out 0x3e, r29 ; 62 608: 0f be out 0x3f, r0 ; 63 60a: cd bf out 0x3d, r28 ; 61 60c: 69 83 std Y+1, r22 ; 0x01 60e: 7a 83 std Y+2, r23 ; 0x02 610: 8b 83 std Y+3, r24 ; 0x03 612: 9c 83 std Y+4, r25 ; 0x04 /* 6 cpu cycles per loop + 20 cycles overhead when a constant is passed. */ __asm__ volatile ( "cp %A0,__zero_reg__ \n\t" \ 614: 89 81 ldd r24, Y+1 ; 0x01 616: 9a 81 ldd r25, Y+2 ; 0x02 618: ab 81 ldd r26, Y+3 ; 0x03 61a: bc 81 ldd r27, Y+4 ; 0x04 61c: 81 15 cp r24, r1 61e: 91 05 cpc r25, r1 620: a1 05 cpc r26, r1 622: b1 05 cpc r27, r1 624: 29 f0 breq .+10 ; 0x630 00000626 : 626: 81 50 subi r24, 0x01 ; 1 628: 90 40 sbci r25, 0x00 ; 0 62a: a0 40 sbci r26, 0x00 ; 0 62c: b0 40 sbci r27, 0x00 ; 0 62e: d9 f7 brne .-10 ; 0x626 00000630 : "cpc %B0,__zero_reg__ \n\t" \ "cpc %C0,__zero_reg__ \n\t" \ "cpc %D0,__zero_reg__ \n\t" \ "breq L_EXIT_%= \n\t" \ "L_%=: \n\t" \ "subi %A0,lo8(-(-1)) \n\t" \ "sbci %B0,hi8(-(-1)) \n\t" \ "sbci %C0,hlo8(-(-1)) \n\t" \ "sbci %D0,hhi8(-(-1)) \n\t" \ "brne L_%= \n\t" \ "L_EXIT_%=: \n\t" \ : /* NO OUTPUT */ \ : "w" (number_of_loops) \ ); \ return; } 630: 24 96 adiw r28, 0x04 ; 4 632: 0f b6 in r0, 0x3f ; 63 634: f8 94 cli 636: de bf out 0x3e, r29 ; 62 638: 0f be out 0x3f, r0 ; 63 63a: cd bf out 0x3d, r28 ; 61 63c: df 91 pop r29 63e: cf 91 pop r28 640: 08 95 ret 00000642 : volatile static voidFuncPtru08 UartRxFunc; //! enable and initialize the uart void uartInit(void) { 642: cf 93 push r28 644: df 93 push r29 646: cd b7 in r28, 0x3d ; 61 648: de b7 in r29, 0x3e ; 62 // initialize the buffers uartInitBuffers(); 64a: 19 d0 rcall .+50 ; 0x67e // initialize user receive handler UartRxFunc = 0; 64c: 10 92 e1 00 sts 0x00E1, r1 650: 10 92 e0 00 sts 0x00E0, r1 // enable RxD/TxD and interrupts #ifdef UCR // this line for AT90S8515,8535,ATmega103,etc outb(UCR, BV(RXCIE)|BV(TXCIE)|BV(RXEN)|BV(TXEN)); 654: 88 ed ldi r24, 0xD8 ; 216 656: 80 93 2a 00 sts 0x002A, r24 #endif #ifdef UCSRB // this line for the Mega163 outb(UCSRB, BV(RXCIE)|BV(TXCIE)|BV(RXEN)|BV(TXEN)); #endif #ifdef UCSR0B // this line for dual-uart proessors like the Mega161/Mega128 outb(UCSR0B, BV(RXCIE)|BV(TXCIE)|BV(RXEN)|BV(TXEN)); #endif // set default baud rate uartSetBaudRate(UART_DEFAULT_BAUD_RATE); 65a: 60 e8 ldi r22, 0x80 ; 128 65c: 75 e2 ldi r23, 0x25 ; 37 65e: 80 e0 ldi r24, 0x00 ; 0 660: 90 e0 ldi r25, 0x00 ; 0 662: 3d d0 rcall .+122 ; 0x6de // initialize states uartReadyTx = TRUE; 664: 8f ef ldi r24, 0xFF ; 255 666: 80 93 e2 00 sts 0x00E2, r24 uartBufferedTx = FALSE; 66a: 10 92 eb 00 sts 0x00EB, r1 // clear overflow count uartRxOverflow = 0; 66e: 10 92 f5 00 sts 0x00F5, r1 672: 10 92 f4 00 sts 0x00F4, r1 // enable interrupts sei(); 676: 78 94 sei } 678: df 91 pop r29 67a: cf 91 pop r28 67c: 08 95 ret 0000067e : //! create and initialize the uart transmit and receive buffers void uartInitBuffers(void) { 67e: cf 93 push r28 680: df 93 push r29 682: cd b7 in r28, 0x3d ; 61 684: de b7 in r29, 0x3e ; 62 #ifndef UART_BUFFERS_EXTERNAL_RAM // initialize the UART receive buffer bufferInit(&uartRxBuffer, uartRxData, UART_RX_BUFFER_SIZE); 686: 40 e4 ldi r20, 0x40 ; 64 688: 50 e0 ldi r21, 0x00 ; 0 68a: 60 e6 ldi r22, 0x60 ; 96 68c: 70 e0 ldi r23, 0x00 ; 0 68e: 83 ee ldi r24, 0xE3 ; 227 690: 90 e0 ldi r25, 0x00 ; 0 692: be d1 rcall .+892 ; 0xa10 // initialize the UART transmit buffer bufferInit(&uartTxBuffer, uartTxData, UART_TX_BUFFER_SIZE); 694: 40 e4 ldi r20, 0x40 ; 64 696: 50 e0 ldi r21, 0x00 ; 0 698: 60 ea ldi r22, 0xA0 ; 160 69a: 70 e0 ldi r23, 0x00 ; 0 69c: 8c ee ldi r24, 0xEC ; 236 69e: 90 e0 ldi r25, 0x00 ; 0 6a0: b7 d1 rcall .+878 ; 0xa10 #else // initialize the UART receive buffer bufferInit(&uartRxBuffer, (u08*) UART_RX_BUFFER_ADDR, UART_RX_BUFFER_SIZE); // initialize the UART transmit buffer bufferInit(&uartTxBuffer, (u08*) UART_TX_BUFFER_ADDR, UART_TX_BUFFER_SIZE); #endif } 6a2: df 91 pop r29 6a4: cf 91 pop r28 6a6: 08 95 ret 000006a8 : //! redirects received data to a user function void uartSetRxHandler(void (*rx_func)(unsigned char c)) { 6a8: cf 93 push r28 6aa: df 93 push r29 6ac: cd b7 in r28, 0x3d ; 61 6ae: de b7 in r29, 0x3e ; 62 6b0: 22 97 sbiw r28, 0x02 ; 2 6b2: 0f b6 in r0, 0x3f ; 63 6b4: f8 94 cli 6b6: de bf out 0x3e, r29 ; 62 6b8: 0f be out 0x3f, r0 ; 63 6ba: cd bf out 0x3d, r28 ; 61 6bc: 89 83 std Y+1, r24 ; 0x01 6be: 9a 83 std Y+2, r25 ; 0x02 // set the receive interrupt to run the supplied user function UartRxFunc = rx_func; 6c0: 89 81 ldd r24, Y+1 ; 0x01 6c2: 9a 81 ldd r25, Y+2 ; 0x02 6c4: 90 93 e1 00 sts 0x00E1, r25 6c8: 80 93 e0 00 sts 0x00E0, r24 } 6cc: 22 96 adiw r28, 0x02 ; 2 6ce: 0f b6 in r0, 0x3f ; 63 6d0: f8 94 cli 6d2: de bf out 0x3e, r29 ; 62 6d4: 0f be out 0x3f, r0 ; 63 6d6: cd bf out 0x3d, r28 ; 61 6d8: df 91 pop r29 6da: cf 91 pop r28 6dc: 08 95 ret 000006de : //! set the uart baud rate void uartSetBaudRate(u32 baudrate) { 6de: ef 92 push r14 6e0: ff 92 push r15 6e2: 0f 93 push r16 6e4: 1f 93 push r17 6e6: cf 93 push r28 6e8: df 93 push r29 6ea: cd b7 in r28, 0x3d ; 61 6ec: de b7 in r29, 0x3e ; 62 6ee: 24 97 sbiw r28, 0x04 ; 4 6f0: 0f b6 in r0, 0x3f ; 63 6f2: f8 94 cli 6f4: de bf out 0x3e, r29 ; 62 6f6: 0f be out 0x3f, r0 ; 63 6f8: cd bf out 0x3d, r28 ; 61 6fa: 69 83 std Y+1, r22 ; 0x01 6fc: 7a 83 std Y+2, r23 ; 0x02 6fe: 8b 83 std Y+3, r24 ; 0x03 700: 9c 83 std Y+4, r25 ; 0x04 // calculate division factor for requested baud rate, and set it outb(UBRR, (u08)((F_CPU+(baudrate*8L))/(baudrate*16L)-1)); 702: 89 81 ldd r24, Y+1 ; 0x01 704: 9a 81 ldd r25, Y+2 ; 0x02 706: ab 81 ldd r26, Y+3 ; 0x03 708: bc 81 ldd r27, Y+4 ; 0x04 70a: 68 94 set 70c: 12 f8 bld r1, 2 70e: 88 0f add r24, r24 710: 99 1f adc r25, r25 712: aa 1f adc r26, r26 714: bb 1f adc r27, r27 716: 16 94 lsr r1 718: d1 f7 brne .-12 ; 0x70e 71a: 0f 2e mov r0, r31 71c: f0 e0 ldi r31, 0x00 ; 0 71e: ef 2e mov r14, r31 720: f0 e8 ldi r31, 0x80 ; 128 722: ff 2e mov r15, r31 724: f0 e7 ldi r31, 0x70 ; 112 726: 0f 2f mov r16, r31 728: f0 e0 ldi r31, 0x00 ; 0 72a: 1f 2f mov r17, r31 72c: f0 2d mov r31, r0 72e: e8 0e add r14, r24 730: f9 1e adc r15, r25 732: 0a 1f adc r16, r26 734: 1b 1f adc r17, r27 736: 89 81 ldd r24, Y+1 ; 0x01 738: 9a 81 ldd r25, Y+2 ; 0x02 73a: ab 81 ldd r26, Y+3 ; 0x03 73c: bc 81 ldd r27, Y+4 ; 0x04 73e: 28 2f mov r18, r24 740: 39 2f mov r19, r25 742: 4a 2f mov r20, r26 744: 5b 2f mov r21, r27 746: 68 94 set 748: 13 f8 bld r1, 3 74a: 22 0f add r18, r18 74c: 33 1f adc r19, r19 74e: 44 1f adc r20, r20 750: 55 1f adc r21, r21 752: 16 94 lsr r1 754: d1 f7 brne .-12 ; 0x74a 756: 91 2f mov r25, r17 758: 80 2f mov r24, r16 75a: 7f 2d mov r23, r15 75c: 6e 2d mov r22, r14 75e: 69 d3 rcall .+1746 ; 0xe32 760: b5 2f mov r27, r21 762: a4 2f mov r26, r20 764: 93 2f mov r25, r19 766: 82 2f mov r24, r18 768: 81 50 subi r24, 0x01 ; 1 76a: 80 93 29 00 sts 0x0029, r24 } 76e: 24 96 adiw r28, 0x04 ; 4 770: 0f b6 in r0, 0x3f ; 63 772: f8 94 cli 774: de bf out 0x3e, r29 ; 62 776: 0f be out 0x3f, r0 ; 63 778: cd bf out 0x3d, r28 ; 61 77a: df 91 pop r29 77c: cf 91 pop r28 77e: 1f 91 pop r17 780: 0f 91 pop r16 782: ff 90 pop r15 784: ef 90 pop r14 786: 08 95 ret 00000788 : //! returns the receive buffer structure cBuffer* uartGetRxBuffer(void) { 788: cf 93 push r28 78a: df 93 push r29 78c: cd b7 in r28, 0x3d ; 61 78e: de b7 in r29, 0x3e ; 62 // return rx buffer pointer return &uartRxBuffer; 790: 83 ee ldi r24, 0xE3 ; 227 792: 90 e0 ldi r25, 0x00 ; 0 } 794: df 91 pop r29 796: cf 91 pop r28 798: 08 95 ret 0000079a : //! returns the transmit buffer structure cBuffer* uartGetTxBuffer(void) { 79a: cf 93 push r28 79c: df 93 push r29 79e: cd b7 in r28, 0x3d ; 61 7a0: de b7 in r29, 0x3e ; 62 // return tx buffer pointer return &uartTxBuffer; 7a2: 8c ee ldi r24, 0xEC ; 236 7a4: 90 e0 ldi r25, 0x00 ; 0 } 7a6: df 91 pop r29 7a8: cf 91 pop r28 7aa: 08 95 ret 000007ac : //! transmits a byte over the uart void uartSendByte(u08 txData) { 7ac: cf 93 push r28 7ae: df 93 push r29 7b0: cd b7 in r28, 0x3d ; 61 7b2: de b7 in r29, 0x3e ; 62 7b4: 21 97 sbiw r28, 0x01 ; 1 7b6: 0f b6 in r0, 0x3f ; 63 7b8: f8 94 cli 7ba: de bf out 0x3e, r29 ; 62 7bc: 0f be out 0x3f, r0 ; 63 7be: cd bf out 0x3d, r28 ; 61 7c0: 89 83 std Y+1, r24 ; 0x01 // wait for the transmitter to be ready while(!uartReadyTx); 7c2: 80 91 e2 00 lds r24, 0x00E2 7c6: 88 23 and r24, r24 7c8: e1 f3 breq .-8 ; 0x7c2 // send byte outp( txData, UDR ); 7ca: 89 81 ldd r24, Y+1 ; 0x01 7cc: 80 93 2c 00 sts 0x002C, r24 // set ready state to FALSE uartReadyTx = FALSE; 7d0: 10 92 e2 00 sts 0x00E2, r1 } 7d4: 21 96 adiw r28, 0x01 ; 1 7d6: 0f b6 in r0, 0x3f ; 63 7d8: f8 94 cli 7da: de bf out 0x3e, r29 ; 62 7dc: 0f be out 0x3f, r0 ; 63 7de: cd bf out 0x3d, r28 ; 61 7e0: df 91 pop r29 7e2: cf 91 pop r28 7e4: 08 95 ret 000007e6 : //! gets a byte (if available) from the uart receive buffer u08 uartReceiveByte(u08* rxData) { 7e6: cf 93 push r28 7e8: df 93 push r29 7ea: cd b7 in r28, 0x3d ; 61 7ec: de b7 in r29, 0x3e ; 62 7ee: 24 97 sbiw r28, 0x04 ; 4 7f0: 0f b6 in r0, 0x3f ; 63 7f2: f8 94 cli 7f4: de bf out 0x3e, r29 ; 62 7f6: 0f be out 0x3f, r0 ; 63 7f8: cd bf out 0x3d, r28 ; 61 7fa: 89 83 std Y+1, r24 ; 0x01 7fc: 9a 83 std Y+2, r25 ; 0x02 // make sure we have a receive buffer if(uartRxBuffer.size) 7fe: 80 91 e5 00 lds r24, 0x00E5 802: 90 91 e6 00 lds r25, 0x00E6 806: 00 97 sbiw r24, 0x00 ; 0 808: a1 f0 breq .+40 ; 0x832 { // make sure we have data if(uartRxBuffer.datalength) 80a: 80 91 e7 00 lds r24, 0x00E7 80e: 90 91 e8 00 lds r25, 0x00E8 812: 00 97 sbiw r24, 0x00 ; 0 814: 59 f0 breq .+22 ; 0x82c { // get byte from beginning of buffer *rxData = bufferGetFromFront(&uartRxBuffer); 816: 83 ee ldi r24, 0xE3 ; 227 818: 90 e0 ldi r25, 0x00 ; 0 81a: 27 d1 rcall .+590 ; 0xa6a 81c: e9 81 ldd r30, Y+1 ; 0x01 81e: fa 81 ldd r31, Y+2 ; 0x02 820: 80 83 st Z, r24 return TRUE; 822: 8f ef ldi r24, 0xFF ; 255 824: 90 e0 ldi r25, 0x00 ; 0 826: 8b 83 std Y+3, r24 ; 0x03 828: 9c 83 std Y+4, r25 ; 0x04 82a: 05 c0 rjmp .+10 ; 0x836 } else { // no data return FALSE; 82c: 1b 82 std Y+3, r1 ; 0x03 82e: 1c 82 std Y+4, r1 ; 0x04 830: 02 c0 rjmp .+4 ; 0x836 } } else { // no buffer return FALSE; 832: 1b 82 std Y+3, r1 ; 0x03 834: 1c 82 std Y+4, r1 ; 0x04 } } 836: 8b 81 ldd r24, Y+3 ; 0x03 838: 9c 81 ldd r25, Y+4 ; 0x04 83a: 24 96 adiw r28, 0x04 ; 4 83c: 0f b6 in r0, 0x3f ; 63 83e: f8 94 cli 840: de bf out 0x3e, r29 ; 62 842: 0f be out 0x3f, r0 ; 63 844: cd bf out 0x3d, r28 ; 61 846: df 91 pop r29 848: cf 91 pop r28 84a: 08 95 ret 0000084c : //! flush all data out of the receive buffer void uartFlushReceiveBuffer(void) { 84c: cf 93 push r28 84e: df 93 push r29 850: cd b7 in r28, 0x3d ; 61 852: de b7 in r29, 0x3e ; 62 // flush all data from receive buffer //bufferFlush(&uartRxBuffer); // same effect as above uartRxBuffer.datalength = 0; 854: 10 92 e8 00 sts 0x00E8, r1 858: 10 92 e7 00 sts 0x00E7, r1 } 85c: df 91 pop r29 85e: cf 91 pop r28 860: 08 95 ret 00000862 : //! return true if uart receive buffer is empty u08 uartReceiveBufferIsEmpty(void) { 862: cf 93 push r28 864: df 93 push r29 866: cd b7 in r28, 0x3d ; 61 868: de b7 in r29, 0x3e ; 62 86a: 22 97 sbiw r28, 0x02 ; 2 86c: 0f b6 in r0, 0x3f ; 63 86e: f8 94 cli 870: de bf out 0x3e, r29 ; 62 872: 0f be out 0x3f, r0 ; 63 874: cd bf out 0x3d, r28 ; 61 if(uartRxBuffer.datalength == 0) 876: 80 91 e7 00 lds r24, 0x00E7 87a: 90 91 e8 00 lds r25, 0x00E8 87e: 00 97 sbiw r24, 0x00 ; 0 880: 29 f4 brne .+10 ; 0x88c { return TRUE; 882: 8f ef ldi r24, 0xFF ; 255 884: 90 e0 ldi r25, 0x00 ; 0 886: 89 83 std Y+1, r24 ; 0x01 888: 9a 83 std Y+2, r25 ; 0x02 88a: 02 c0 rjmp .+4 ; 0x890 } else { return FALSE; 88c: 19 82 std Y+1, r1 ; 0x01 88e: 1a 82 std Y+2, r1 ; 0x02 } } 890: 89 81 ldd r24, Y+1 ; 0x01 892: 9a 81 ldd r25, Y+2 ; 0x02 894: 22 96 adiw r28, 0x02 ; 2 896: 0f b6 in r0, 0x3f ; 63 898: f8 94 cli 89a: de bf out 0x3e, r29 ; 62 89c: 0f be out 0x3f, r0 ; 63 89e: cd bf out 0x3d, r28 ; 61 8a0: df 91 pop r29 8a2: cf 91 pop r28 8a4: 08 95 ret 000008a6 : //! add byte to end of uart Tx buffer void uartAddToTxBuffer(u08 data) { 8a6: cf 93 push r28 8a8: df 93 push r29 8aa: cd b7 in r28, 0x3d ; 61 8ac: de b7 in r29, 0x3e ; 62 8ae: 21 97 sbiw r28, 0x01 ; 1 8b0: 0f b6 in r0, 0x3f ; 63 8b2: f8 94 cli 8b4: de bf out 0x3e, r29 ; 62 8b6: 0f be out 0x3f, r0 ; 63 8b8: cd bf out 0x3d, r28 ; 61 8ba: 89 83 std Y+1, r24 ; 0x01 // add data byte to the end of the tx buffer bufferAddToEnd(&uartTxBuffer, data); 8bc: 69 81 ldd r22, Y+1 ; 0x01 8be: 8c ee ldi r24, 0xEC ; 236 8c0: 90 e0 ldi r25, 0x00 ; 0 8c2: dc d1 rcall .+952 ; 0xc7c } 8c4: 21 96 adiw r28, 0x01 ; 1 8c6: 0f b6 in r0, 0x3f ; 63 8c8: f8 94 cli 8ca: de bf out 0x3e, r29 ; 62 8cc: 0f be out 0x3f, r0 ; 63 8ce: cd bf out 0x3d, r28 ; 61 8d0: df 91 pop r29 8d2: cf 91 pop r28 8d4: 08 95 ret 000008d6 : //! start transmission of the current uart Tx buffer contents void uartSendTxBuffer(void) { 8d6: cf 93 push r28 8d8: df 93 push r29 8da: cd b7 in r28, 0x3d ; 61 8dc: de b7 in r29, 0x3e ; 62 // turn on buffered transmit uartBufferedTx = TRUE; 8de: 8f ef ldi r24, 0xFF ; 255 8e0: 80 93 eb 00 sts 0x00EB, r24 // send the first byte to get things going by interrupts uartSendByte(bufferGetFromFront(&uartTxBuffer)); 8e4: 8c ee ldi r24, 0xEC ; 236 8e6: 90 e0 ldi r25, 0x00 ; 0 8e8: c0 d0 rcall .+384 ; 0xa6a 8ea: 60 df rcall .-320 ; 0x7ac } 8ec: df 91 pop r29 8ee: cf 91 pop r28 8f0: 08 95 ret 000008f2 <__vector_11>: //! UART Transmit Complete Interrupt Handler UART_INTERRUPT_HANDLER(SIG_UART_TRANS) { 8f2: 1f 92 push r1 8f4: 0f 92 push r0 8f6: 0f b6 in r0, 0x3f ; 63 8f8: 0f 92 push r0 8fa: 11 24 eor r1, r1 8fc: 2f 93 push r18 8fe: 3f 93 push r19 900: 4f 93 push r20 902: 5f 93 push r21 904: 6f 93 push r22 906: 7f 93 push r23 908: 8f 93 push r24 90a: 9f 93 push r25 90c: af 93 push r26 90e: bf 93 push r27 910: ef 93 push r30 912: ff 93 push r31 914: cf 93 push r28 916: df 93 push r29 918: cd b7 in r28, 0x3d ; 61 91a: de b7 in r29, 0x3e ; 62 // check if buffered tx is enabled if(uartBufferedTx) 91c: 80 91 eb 00 lds r24, 0x00EB 920: 88 23 and r24, r24 922: 91 f0 breq .+36 ; 0x948 { // check if there's data left in the buffer if(uartTxBuffer.datalength) 924: 80 91 f0 00 lds r24, 0x00F0 928: 90 91 f1 00 lds r25, 0x00F1 92c: 00 97 sbiw r24, 0x00 ; 0 92e: 31 f0 breq .+12 ; 0x93c { // send byte from top of buffer outp( bufferGetFromFront(&uartTxBuffer), UDR ); 930: 8c ee ldi r24, 0xEC ; 236 932: 90 e0 ldi r25, 0x00 ; 0 934: 9a d0 rcall .+308 ; 0xa6a 936: 80 93 2c 00 sts 0x002C, r24 93a: 09 c0 rjmp .+18 ; 0x94e } else { // no data left uartBufferedTx = FALSE; 93c: 10 92 eb 00 sts 0x00EB, r1 // return to ready state uartReadyTx = TRUE; 940: 8f ef ldi r24, 0xFF ; 255 942: 80 93 e2 00 sts 0x00E2, r24 946: 03 c0 rjmp .+6 ; 0x94e } } else { // we're using single-byte tx mode // indicate transmit complete, back to ready uartReadyTx = TRUE; 948: 8f ef ldi r24, 0xFF ; 255 94a: 80 93 e2 00 sts 0x00E2, r24 } } 94e: df 91 pop r29 950: cf 91 pop r28 952: ff 91 pop r31 954: ef 91 pop r30 956: bf 91 pop r27 958: af 91 pop r26 95a: 9f 91 pop r25 95c: 8f 91 pop r24 95e: 7f 91 pop r23 960: 6f 91 pop r22 962: 5f 91 pop r21 964: 4f 91 pop r20 966: 3f 91 pop r19 968: 2f 91 pop r18 96a: 0f 90 pop r0 96c: 0f be out 0x3f, r0 ; 63 96e: 0f 90 pop r0 970: 1f 90 pop r1 972: 18 95 reti 00000974 <__vector_9>: //! UART Receive Complete Interrupt Handler UART_INTERRUPT_HANDLER(SIG_UART_RECV) { 974: 1f 92 push r1 976: 0f 92 push r0 978: 0f b6 in r0, 0x3f ; 63 97a: 0f 92 push r0 97c: 11 24 eor r1, r1 97e: 2f 93 push r18 980: 3f 93 push r19 982: 4f 93 push r20 984: 5f 93 push r21 986: 6f 93 push r22 988: 7f 93 push r23 98a: 8f 93 push r24 98c: 9f 93 push r25 98e: af 93 push r26 990: bf 93 push r27 992: ef 93 push r30 994: ff 93 push r31 996: cf 93 push r28 998: df 93 push r29 99a: cd b7 in r28, 0x3d ; 61 99c: de b7 in r29, 0x3e ; 62 99e: 21 97 sbiw r28, 0x01 ; 1 9a0: de bf out 0x3e, r29 ; 62 9a2: cd bf out 0x3d, r28 ; 61 u08 c; // get received char c = inp(UDR); 9a4: 80 91 2c 00 lds r24, 0x002C 9a8: 89 83 std Y+1, r24 ; 0x01 // if there's a user function to handle this receive event if(UartRxFunc) 9aa: 80 91 e0 00 lds r24, 0x00E0 9ae: 90 91 e1 00 lds r25, 0x00E1 9b2: 00 97 sbiw r24, 0x00 ; 0 9b4: 39 f0 breq .+14 ; 0x9c4 { // call it and pass the received data UartRxFunc(c); 9b6: e0 91 e0 00 lds r30, 0x00E0 9ba: f0 91 e1 00 lds r31, 0x00E1 9be: 89 81 ldd r24, Y+1 ; 0x01 9c0: 09 95 icall 9c2: 0f c0 rjmp .+30 ; 0x9e2 } else { // otherwise do default processing // put received char in buffer // check if there's space if( !bufferAddToEnd(&uartRxBuffer, c) ) 9c4: 69 81 ldd r22, Y+1 ; 0x01 9c6: 83 ee ldi r24, 0xE3 ; 227 9c8: 90 e0 ldi r25, 0x00 ; 0 9ca: 58 d1 rcall .+688 ; 0xc7c 9cc: 88 23 and r24, r24 9ce: 49 f4 brne .+18 ; 0x9e2 { // no space in buffer // count overflow uartRxOverflow++; 9d0: 80 91 f4 00 lds r24, 0x00F4 9d4: 90 91 f5 00 lds r25, 0x00F5 9d8: 01 96 adiw r24, 0x01 ; 1 9da: 90 93 f5 00 sts 0x00F5, r25 9de: 80 93 f4 00 sts 0x00F4, r24 } } } 9e2: 21 96 adiw r28, 0x01 ; 1 9e4: f8 94 cli 9e6: de bf out 0x3e, r29 ; 62 9e8: cd bf out 0x3d, r28 ; 61 9ea: df 91 pop r29 9ec: cf 91 pop r28 9ee: ff 91 pop r31 9f0: ef 91 pop r30 9f2: bf 91 pop r27 9f4: af 91 pop r26 9f6: 9f 91 pop r25 9f8: 8f 91 pop r24 9fa: 7f 91 pop r23 9fc: 6f 91 pop r22 9fe: 5f 91 pop r21 a00: 4f 91 pop r20 a02: 3f 91 pop r19 a04: 2f 91 pop r18 a06: 0f 90 pop r0 a08: 0f be out 0x3f, r0 ; 63 a0a: 0f 90 pop r0 a0c: 1f 90 pop r1 a0e: 18 95 reti 00000a10 : // initialization void bufferInit(cBuffer* buffer, unsigned char *start, unsigned short size) { a10: cf 93 push r28 a12: df 93 push r29 a14: cd b7 in r28, 0x3d ; 61 a16: de b7 in r29, 0x3e ; 62 a18: 26 97 sbiw r28, 0x06 ; 6 a1a: 0f b6 in r0, 0x3f ; 63 a1c: f8 94 cli a1e: de bf out 0x3e, r29 ; 62 a20: 0f be out 0x3f, r0 ; 63 a22: cd bf out 0x3d, r28 ; 61 a24: 89 83 std Y+1, r24 ; 0x01 a26: 9a 83 std Y+2, r25 ; 0x02 a28: 6b 83 std Y+3, r22 ; 0x03 a2a: 7c 83 std Y+4, r23 ; 0x04 a2c: 4d 83 std Y+5, r20 ; 0x05 a2e: 5e 83 std Y+6, r21 ; 0x06 // set start pointer of the buffer buffer->dataptr = start; a30: e9 81 ldd r30, Y+1 ; 0x01 a32: fa 81 ldd r31, Y+2 ; 0x02 a34: 8b 81 ldd r24, Y+3 ; 0x03 a36: 9c 81 ldd r25, Y+4 ; 0x04 a38: 80 83 st Z, r24 a3a: 91 83 std Z+1, r25 ; 0x01 buffer->size = size; a3c: e9 81 ldd r30, Y+1 ; 0x01 a3e: fa 81 ldd r31, Y+2 ; 0x02 a40: 8d 81 ldd r24, Y+5 ; 0x05 a42: 9e 81 ldd r25, Y+6 ; 0x06 a44: 82 83 std Z+2, r24 ; 0x02 a46: 93 83 std Z+3, r25 ; 0x03 // initialize index and length buffer->dataindex = 0; a48: e9 81 ldd r30, Y+1 ; 0x01 a4a: fa 81 ldd r31, Y+2 ; 0x02 a4c: 16 82 std Z+6, r1 ; 0x06 a4e: 17 82 std Z+7, r1 ; 0x07 buffer->datalength = 0; a50: e9 81 ldd r30, Y+1 ; 0x01 a52: fa 81 ldd r31, Y+2 ; 0x02 a54: 14 82 std Z+4, r1 ; 0x04 a56: 15 82 std Z+5, r1 ; 0x05 } a58: 26 96 adiw r28, 0x06 ; 6 a5a: 0f b6 in r0, 0x3f ; 63 a5c: f8 94 cli a5e: de bf out 0x3e, r29 ; 62 a60: 0f be out 0x3f, r0 ; 63 a62: cd bf out 0x3d, r28 ; 61 a64: df 91 pop r29 a66: cf 91 pop r28 a68: 08 95 ret 00000a6a : // access routines unsigned char bufferGetFromFront(cBuffer* buffer) { a6a: 0f 93 push r16 a6c: 1f 93 push r17 a6e: cf 93 push r28 a70: df 93 push r29 a72: cd b7 in r28, 0x3d ; 61 a74: de b7 in r29, 0x3e ; 62 a76: 23 97 sbiw r28, 0x03 ; 3 a78: 0f b6 in r0, 0x3f ; 63 a7a: f8 94 cli a7c: de bf out 0x3e, r29 ; 62 a7e: 0f be out 0x3f, r0 ; 63 a80: cd bf out 0x3d, r28 ; 61 a82: 89 83 std Y+1, r24 ; 0x01 a84: 9a 83 std Y+2, r25 ; 0x02 unsigned char data = 0; a86: 1b 82 std Y+3, r1 ; 0x03 // check to see if there's data in the buffer if(buffer->datalength) a88: e9 81 ldd r30, Y+1 ; 0x01 a8a: fa 81 ldd r31, Y+2 ; 0x02 a8c: 84 81 ldd r24, Z+4 ; 0x04 a8e: 95 81 ldd r25, Z+5 ; 0x05 a90: 00 97 sbiw r24, 0x00 ; 0 a92: 09 f4 brne .+2 ; 0xa96 a94: 46 c0 rjmp .+140 ; 0xb22 { // get the first character from buffer data = buffer->dataptr[buffer->dataindex]; a96: e9 81 ldd r30, Y+1 ; 0x01 a98: fa 81 ldd r31, Y+2 ; 0x02 a9a: a9 81 ldd r26, Y+1 ; 0x01 a9c: ba 81 ldd r27, Y+2 ; 0x02 a9e: 20 81 ld r18, Z aa0: 31 81 ldd r19, Z+1 ; 0x01 aa2: fb 2f mov r31, r27 aa4: ea 2f mov r30, r26 aa6: 86 81 ldd r24, Z+6 ; 0x06 aa8: 97 81 ldd r25, Z+7 ; 0x07 aaa: f3 2f mov r31, r19 aac: e2 2f mov r30, r18 aae: e8 0f add r30, r24 ab0: f9 1f adc r31, r25 ab2: 80 81 ld r24, Z ab4: 8b 83 std Y+3, r24 ; 0x03 // move index down and decrement length buffer->dataindex++; ab6: a9 81 ldd r26, Y+1 ; 0x01 ab8: ba 81 ldd r27, Y+2 ; 0x02 aba: e9 81 ldd r30, Y+1 ; 0x01 abc: fa 81 ldd r31, Y+2 ; 0x02 abe: 86 81 ldd r24, Z+6 ; 0x06 ac0: 97 81 ldd r25, Z+7 ; 0x07 ac2: 01 96 adiw r24, 0x01 ; 1 ac4: fb 2f mov r31, r27 ac6: ea 2f mov r30, r26 ac8: 86 83 std Z+6, r24 ; 0x06 aca: 97 83 std Z+7, r25 ; 0x07 if(buffer->dataindex >= buffer->size) acc: e9 81 ldd r30, Y+1 ; 0x01 ace: fa 81 ldd r31, Y+2 ; 0x02 ad0: a9 81 ldd r26, Y+1 ; 0x01 ad2: ba 81 ldd r27, Y+2 ; 0x02 ad4: 26 81 ldd r18, Z+6 ; 0x06 ad6: 37 81 ldd r19, Z+7 ; 0x07 ad8: fb 2f mov r31, r27 ada: ea 2f mov r30, r26 adc: 82 81 ldd r24, Z+2 ; 0x02 ade: 93 81 ldd r25, Z+3 ; 0x03 ae0: 28 17 cp r18, r24 ae2: 39 07 cpc r19, r25 ae4: 98 f0 brcs .+38 ; 0xb0c { buffer->dataindex %= buffer->size; ae6: 09 81 ldd r16, Y+1 ; 0x01 ae8: 1a 81 ldd r17, Y+2 ; 0x02 aea: e9 81 ldd r30, Y+1 ; 0x01 aec: fa 81 ldd r31, Y+2 ; 0x02 aee: a9 81 ldd r26, Y+1 ; 0x01 af0: ba 81 ldd r27, Y+2 ; 0x02 af2: 86 81 ldd r24, Z+6 ; 0x06 af4: 97 81 ldd r25, Z+7 ; 0x07 af6: fb 2f mov r31, r27 af8: ea 2f mov r30, r26 afa: 22 81 ldd r18, Z+2 ; 0x02 afc: 33 81 ldd r19, Z+3 ; 0x03 afe: 73 2f mov r23, r19 b00: 62 2f mov r22, r18 b02: 81 d1 rcall .+770 ; 0xe06 b04: f1 2f mov r31, r17 b06: e0 2f mov r30, r16 b08: 86 83 std Z+6, r24 ; 0x06 b0a: 97 83 std Z+7, r25 ; 0x07 } buffer->datalength--; b0c: a9 81 ldd r26, Y+1 ; 0x01 b0e: ba 81 ldd r27, Y+2 ; 0x02 b10: e9 81 ldd r30, Y+1 ; 0x01 b12: fa 81 ldd r31, Y+2 ; 0x02 b14: 84 81 ldd r24, Z+4 ; 0x04 b16: 95 81 ldd r25, Z+5 ; 0x05 b18: 01 97 sbiw r24, 0x01 ; 1 b1a: fb 2f mov r31, r27 b1c: ea 2f mov r30, r26 b1e: 84 83 std Z+4, r24 ; 0x04 b20: 95 83 std Z+5, r25 ; 0x05 } // return return data; b22: 8b 81 ldd r24, Y+3 ; 0x03 b24: 99 27 eor r25, r25 } b26: 23 96 adiw r28, 0x03 ; 3 b28: 0f b6 in r0, 0x3f ; 63 b2a: f8 94 cli b2c: de bf out 0x3e, r29 ; 62 b2e: 0f be out 0x3f, r0 ; 63 b30: cd bf out 0x3d, r28 ; 61 b32: df 91 pop r29 b34: cf 91 pop r28 b36: 1f 91 pop r17 b38: 0f 91 pop r16 b3a: 08 95 ret 00000b3c : void bufferDumpFromFront(cBuffer* buffer, unsigned short numbytes) { b3c: 0f 93 push r16 b3e: 1f 93 push r17 b40: cf 93 push r28 b42: df 93 push r29 b44: cd b7 in r28, 0x3d ; 61 b46: de b7 in r29, 0x3e ; 62 b48: 24 97 sbiw r28, 0x04 ; 4 b4a: 0f b6 in r0, 0x3f ; 63 b4c: f8 94 cli b4e: de bf out 0x3e, r29 ; 62 b50: 0f be out 0x3f, r0 ; 63 b52: cd bf out 0x3d, r28 ; 61 b54: 89 83 std Y+1, r24 ; 0x01 b56: 9a 83 std Y+2, r25 ; 0x02 b58: 6b 83 std Y+3, r22 ; 0x03 b5a: 7c 83 std Y+4, r23 ; 0x04 // dump numbytes from the front of the buffer // are we dumping less than the entire buffer? if(numbytes < buffer->datalength) b5c: e9 81 ldd r30, Y+1 ; 0x01 b5e: fa 81 ldd r31, Y+2 ; 0x02 b60: 2b 81 ldd r18, Y+3 ; 0x03 b62: 3c 81 ldd r19, Y+4 ; 0x04 b64: 84 81 ldd r24, Z+4 ; 0x04 b66: 95 81 ldd r25, Z+5 ; 0x05 b68: 28 17 cp r18, r24 b6a: 39 07 cpc r19, r25 b6c: 08 f0 brcs .+2 ; 0xb70 b6e: 3f c0 rjmp .+126 ; 0xbee { // move index down by numbytes and decrement length by numbytes buffer->dataindex += numbytes; b70: a9 81 ldd r26, Y+1 ; 0x01 b72: ba 81 ldd r27, Y+2 ; 0x02 b74: e9 81 ldd r30, Y+1 ; 0x01 b76: fa 81 ldd r31, Y+2 ; 0x02 b78: 26 81 ldd r18, Z+6 ; 0x06 b7a: 37 81 ldd r19, Z+7 ; 0x07 b7c: 8b 81 ldd r24, Y+3 ; 0x03 b7e: 9c 81 ldd r25, Y+4 ; 0x04 b80: 82 0f add r24, r18 b82: 93 1f adc r25, r19 b84: fb 2f mov r31, r27 b86: ea 2f mov r30, r26 b88: 86 83 std Z+6, r24 ; 0x06 b8a: 97 83 std Z+7, r25 ; 0x07 if(buffer->dataindex >= buffer->size) b8c: e9 81 ldd r30, Y+1 ; 0x01 b8e: fa 81 ldd r31, Y+2 ; 0x02 b90: a9 81 ldd r26, Y+1 ; 0x01 b92: ba 81 ldd r27, Y+2 ; 0x02 b94: 26 81 ldd r18, Z+6 ; 0x06 b96: 37 81 ldd r19, Z+7 ; 0x07 b98: fb 2f mov r31, r27 b9a: ea 2f mov r30, r26 b9c: 82 81 ldd r24, Z+2 ; 0x02 b9e: 93 81 ldd r25, Z+3 ; 0x03 ba0: 28 17 cp r18, r24 ba2: 39 07 cpc r19, r25 ba4: 98 f0 brcs .+38 ; 0xbcc { buffer->dataindex %= buffer->size; ba6: 09 81 ldd r16, Y+1 ; 0x01 ba8: 1a 81 ldd r17, Y+2 ; 0x02 baa: e9 81 ldd r30, Y+1 ; 0x01 bac: fa 81 ldd r31, Y+2 ; 0x02 bae: a9 81 ldd r26, Y+1 ; 0x01 bb0: ba 81 ldd r27, Y+2 ; 0x02 bb2: 86 81 ldd r24, Z+6 ; 0x06 bb4: 97 81 ldd r25, Z+7 ; 0x07 bb6: fb 2f mov r31, r27 bb8: ea 2f mov r30, r26 bba: 22 81 ldd r18, Z+2 ; 0x02 bbc: 33 81 ldd r19, Z+3 ; 0x03 bbe: 73 2f mov r23, r19 bc0: 62 2f mov r22, r18 bc2: 21 d1 rcall .+578 ; 0xe06 bc4: f1 2f mov r31, r17 bc6: e0 2f mov r30, r16 bc8: 86 83 std Z+6, r24 ; 0x06 bca: 97 83 std Z+7, r25 ; 0x07 } buffer->datalength -= numbytes; bcc: a9 81 ldd r26, Y+1 ; 0x01 bce: ba 81 ldd r27, Y+2 ; 0x02 bd0: e9 81 ldd r30, Y+1 ; 0x01 bd2: fa 81 ldd r31, Y+2 ; 0x02 bd4: 24 81 ldd r18, Z+4 ; 0x04 bd6: 35 81 ldd r19, Z+5 ; 0x05 bd8: 8b 81 ldd r24, Y+3 ; 0x03 bda: 9c 81 ldd r25, Y+4 ; 0x04 bdc: 28 1b sub r18, r24 bde: 39 0b sbc r19, r25 be0: 93 2f mov r25, r19 be2: 82 2f mov r24, r18 be4: fb 2f mov r31, r27 be6: ea 2f mov r30, r26 be8: 84 83 std Z+4, r24 ; 0x04 bea: 95 83 std Z+5, r25 ; 0x05 bec: 04 c0 rjmp .+8 ; 0xbf6 } else { // flush the whole buffer buffer->datalength = 0; bee: e9 81 ldd r30, Y+1 ; 0x01 bf0: fa 81 ldd r31, Y+2 ; 0x02 bf2: 14 82 std Z+4, r1 ; 0x04 bf4: 15 82 std Z+5, r1 ; 0x05 } } bf6: 24 96 adiw r28, 0x04 ; 4 bf8: 0f b6 in r0, 0x3f ; 63 bfa: f8 94 cli bfc: de bf out 0x3e, r29 ; 62 bfe: 0f be out 0x3f, r0 ; 63 c00: cd bf out 0x3d, r28 ; 61 c02: df 91 pop r29 c04: cf 91 pop r28 c06: 1f 91 pop r17 c08: 0f 91 pop r16 c0a: 08 95 ret 00000c0c : unsigned char bufferGetAtIndex(cBuffer* buffer, unsigned short index) { c0c: 0f 93 push r16 c0e: 1f 93 push r17 c10: cf 93 push r28 c12: df 93 push r29 c14: cd b7 in r28, 0x3d ; 61 c16: de b7 in r29, 0x3e ; 62 c18: 24 97 sbiw r28, 0x04 ; 4 c1a: 0f b6 in r0, 0x3f ; 63 c1c: f8 94 cli c1e: de bf out 0x3e, r29 ; 62 c20: 0f be out 0x3f, r0 ; 63 c22: cd bf out 0x3d, r28 ; 61 c24: 89 83 std Y+1, r24 ; 0x01 c26: 9a 83 std Y+2, r25 ; 0x02 c28: 6b 83 std Y+3, r22 ; 0x03 c2a: 7c 83 std Y+4, r23 ; 0x04 // return character at index in buffer return buffer->dataptr[(buffer->dataindex+index)%(buffer->size)]; c2c: 09 81 ldd r16, Y+1 ; 0x01 c2e: 1a 81 ldd r17, Y+2 ; 0x02 c30: e9 81 ldd r30, Y+1 ; 0x01 c32: fa 81 ldd r31, Y+2 ; 0x02 c34: 26 81 ldd r18, Z+6 ; 0x06 c36: 37 81 ldd r19, Z+7 ; 0x07 c38: 8b 81 ldd r24, Y+3 ; 0x03 c3a: 9c 81 ldd r25, Y+4 ; 0x04 c3c: 82 0f add r24, r18 c3e: 93 1f adc r25, r19 c40: e9 81 ldd r30, Y+1 ; 0x01 c42: fa 81 ldd r31, Y+2 ; 0x02 c44: 22 81 ldd r18, Z+2 ; 0x02 c46: 33 81 ldd r19, Z+3 ; 0x03 c48: 73 2f mov r23, r19 c4a: 62 2f mov r22, r18 c4c: dc d0 rcall .+440 ; 0xe06 c4e: 28 2f mov r18, r24 c50: 39 2f mov r19, r25 c52: f1 2f mov r31, r17 c54: e0 2f mov r30, r16 c56: 80 81 ld r24, Z c58: 91 81 ldd r25, Z+1 ; 0x01 c5a: f3 2f mov r31, r19 c5c: e2 2f mov r30, r18 c5e: e8 0f add r30, r24 c60: f9 1f adc r31, r25 c62: 80 81 ld r24, Z c64: 99 27 eor r25, r25 } c66: 24 96 adiw r28, 0x04 ; 4 c68: 0f b6 in r0, 0x3f ; 63 c6a: f8 94 cli c6c: de bf out 0x3e, r29 ; 62 c6e: 0f be out 0x3f, r0 ; 63 c70: cd bf out 0x3d, r28 ; 61 c72: df 91 pop r29 c74: cf 91 pop r28 c76: 1f 91 pop r17 c78: 0f 91 pop r16 c7a: 08 95 ret 00000c7c : unsigned char bufferAddToEnd(cBuffer* buffer, unsigned char data) { c7c: 0f 93 push r16 c7e: 1f 93 push r17 c80: cf 93 push r28 c82: df 93 push r29 c84: cd b7 in r28, 0x3d ; 61 c86: de b7 in r29, 0x3e ; 62 c88: 25 97 sbiw r28, 0x05 ; 5 c8a: 0f b6 in r0, 0x3f ; 63 c8c: f8 94 cli c8e: de bf out 0x3e, r29 ; 62 c90: 0f be out 0x3f, r0 ; 63 c92: cd bf out 0x3d, r28 ; 61 c94: 89 83 std Y+1, r24 ; 0x01 c96: 9a 83 std Y+2, r25 ; 0x02 c98: 6b 83 std Y+3, r22 ; 0x03 // make sure the buffer has room if(buffer->datalength < buffer->size) c9a: e9 81 ldd r30, Y+1 ; 0x01 c9c: fa 81 ldd r31, Y+2 ; 0x02 c9e: a9 81 ldd r26, Y+1 ; 0x01 ca0: ba 81 ldd r27, Y+2 ; 0x02 ca2: 24 81 ldd r18, Z+4 ; 0x04 ca4: 35 81 ldd r19, Z+5 ; 0x05 ca6: fb 2f mov r31, r27 ca8: ea 2f mov r30, r26 caa: 82 81 ldd r24, Z+2 ; 0x02 cac: 93 81 ldd r25, Z+3 ; 0x03 cae: 28 17 cp r18, r24 cb0: 39 07 cpc r19, r25 cb2: 88 f5 brcc .+98 ; 0xd16 { // save data byte at end of buffer buffer->dataptr[(buffer->dataindex + buffer->datalength) % buffer->size] = data; cb4: 09 81 ldd r16, Y+1 ; 0x01 cb6: 1a 81 ldd r17, Y+2 ; 0x02 cb8: e9 81 ldd r30, Y+1 ; 0x01 cba: fa 81 ldd r31, Y+2 ; 0x02 cbc: a9 81 ldd r26, Y+1 ; 0x01 cbe: ba 81 ldd r27, Y+2 ; 0x02 cc0: 26 81 ldd r18, Z+6 ; 0x06 cc2: 37 81 ldd r19, Z+7 ; 0x07 cc4: fb 2f mov r31, r27 cc6: ea 2f mov r30, r26 cc8: 84 81 ldd r24, Z+4 ; 0x04 cca: 95 81 ldd r25, Z+5 ; 0x05 ccc: 82 0f add r24, r18 cce: 93 1f adc r25, r19 cd0: e9 81 ldd r30, Y+1 ; 0x01 cd2: fa 81 ldd r31, Y+2 ; 0x02 cd4: 22 81 ldd r18, Z+2 ; 0x02 cd6: 33 81 ldd r19, Z+3 ; 0x03 cd8: 73 2f mov r23, r19 cda: 62 2f mov r22, r18 cdc: 94 d0 rcall .+296 ; 0xe06 cde: 28 2f mov r18, r24 ce0: 39 2f mov r19, r25 ce2: f1 2f mov r31, r17 ce4: e0 2f mov r30, r16 ce6: 80 81 ld r24, Z ce8: 91 81 ldd r25, Z+1 ; 0x01 cea: f3 2f mov r31, r19 cec: e2 2f mov r30, r18 cee: e8 0f add r30, r24 cf0: f9 1f adc r31, r25 cf2: 8b 81 ldd r24, Y+3 ; 0x03 cf4: 80 83 st Z, r24 // increment the length buffer->datalength++; cf6: a9 81 ldd r26, Y+1 ; 0x01 cf8: ba 81 ldd r27, Y+2 ; 0x02 cfa: e9 81 ldd r30, Y+1 ; 0x01 cfc: fa 81 ldd r31, Y+2 ; 0x02 cfe: 84 81 ldd r24, Z+4 ; 0x04 d00: 95 81 ldd r25, Z+5 ; 0x05 d02: 01 96 adiw r24, 0x01 ; 1 d04: fb 2f mov r31, r27 d06: ea 2f mov r30, r26 d08: 84 83 std Z+4, r24 ; 0x04 d0a: 95 83 std Z+5, r25 ; 0x05 // return success return -1; d0c: 8f ef ldi r24, 0xFF ; 255 d0e: 90 e0 ldi r25, 0x00 ; 0 d10: 8c 83 std Y+4, r24 ; 0x04 d12: 9d 83 std Y+5, r25 ; 0x05 d14: 02 c0 rjmp .+4 ; 0xd1a } else return 0; d16: 1c 82 std Y+4, r1 ; 0x04 d18: 1d 82 std Y+5, r1 ; 0x05 } d1a: 8c 81 ldd r24, Y+4 ; 0x04 d1c: 9d 81 ldd r25, Y+5 ; 0x05 d1e: 25 96 adiw r28, 0x05 ; 5 d20: 0f b6 in r0, 0x3f ; 63 d22: f8 94 cli d24: de bf out 0x3e, r29 ; 62 d26: 0f be out 0x3f, r0 ; 63 d28: cd bf out 0x3d, r28 ; 61 d2a: df 91 pop r29 d2c: cf 91 pop r28 d2e: 1f 91 pop r17 d30: 0f 91 pop r16 d32: 08 95 ret 00000d34 : unsigned char bufferIsNotFull(cBuffer* buffer) { d34: cf 93 push r28 d36: df 93 push r29 d38: cd b7 in r28, 0x3d ; 61 d3a: de b7 in r29, 0x3e ; 62 d3c: 24 97 sbiw r28, 0x04 ; 4 d3e: 0f b6 in r0, 0x3f ; 63 d40: f8 94 cli d42: de bf out 0x3e, r29 ; 62 d44: 0f be out 0x3f, r0 ; 63 d46: cd bf out 0x3d, r28 ; 61 d48: 89 83 std Y+1, r24 ; 0x01 d4a: 9a 83 std Y+2, r25 ; 0x02 // check to see if the buffer has room // return true if there is room return (buffer->datalength < buffer->size); d4c: 1b 82 std Y+3, r1 ; 0x03 d4e: 1c 82 std Y+4, r1 ; 0x04 d50: e9 81 ldd r30, Y+1 ; 0x01 d52: fa 81 ldd r31, Y+2 ; 0x02 d54: a9 81 ldd r26, Y+1 ; 0x01 d56: ba 81 ldd r27, Y+2 ; 0x02 d58: 24 81 ldd r18, Z+4 ; 0x04 d5a: 35 81 ldd r19, Z+5 ; 0x05 d5c: fb 2f mov r31, r27 d5e: ea 2f mov r30, r26 d60: 82 81 ldd r24, Z+2 ; 0x02 d62: 93 81 ldd r25, Z+3 ; 0x03 d64: 28 17 cp r18, r24 d66: 39 07 cpc r19, r25 d68: 20 f4 brcc .+8 ; 0xd72 d6a: 81 e0 ldi r24, 0x01 ; 1 d6c: 90 e0 ldi r25, 0x00 ; 0 d6e: 8b 83 std Y+3, r24 ; 0x03 d70: 9c 83 std Y+4, r25 ; 0x04 d72: 8b 81 ldd r24, Y+3 ; 0x03 d74: 9c 81 ldd r25, Y+4 ; 0x04 } d76: 24 96 adiw r28, 0x04 ; 4 d78: 0f b6 in r0, 0x3f ; 63 d7a: f8 94 cli d7c: de bf out 0x3e, r29 ; 62 d7e: 0f be out 0x3f, r0 ; 63 d80: cd bf out 0x3d, r28 ; 61 d82: df 91 pop r29 d84: cf 91 pop r28 d86: 08 95 ret 00000d88 : void bufferFlush(cBuffer* buffer) { d88: cf 93 push r28 d8a: df 93 push r29 d8c: cd b7 in r28, 0x3d ; 61 d8e: de b7 in r29, 0x3e ; 62 d90: 22 97 sbiw r28, 0x02 ; 2 d92: 0f b6 in r0, 0x3f ; 63 d94: f8 94 cli d96: de bf out 0x3e, r29 ; 62 d98: 0f be out 0x3f, r0 ; 63 d9a: cd bf out 0x3d, r28 ; 61 d9c: 89 83 std Y+1, r24 ; 0x01 d9e: 9a 83 std Y+2, r25 ; 0x02 // flush contents of the buffer buffer->datalength = 0; da0: e9 81 ldd r30, Y+1 ; 0x01 da2: fa 81 ldd r31, Y+2 ; 0x02 da4: 14 82 std Z+4, r1 ; 0x04 da6: 15 82 std Z+5, r1 ; 0x05 } da8: 22 96 adiw r28, 0x02 ; 2 daa: 0f b6 in r0, 0x3f ; 63 dac: f8 94 cli dae: de bf out 0x3e, r29 ; 62 db0: 0f be out 0x3f, r0 ; 63 db2: cd bf out 0x3d, r28 ; 61 db4: df 91 pop r29 db6: cf 91 pop r28 db8: 08 95 ret 00000dba : dba: e6 2f mov r30, r22 dbc: f7 2f mov r31, r23 dbe: a8 2f mov r26, r24 dc0: b9 2f mov r27, r25 dc2: 02 c0 rjmp .+4 ; 0xdc8 00000dc4 <.memcpy_loop>: dc4: 01 90 ld r0, Z+ dc6: 0d 92 st X+, r0 00000dc8 <.memcpy_start>: dc8: 41 50 subi r20, 0x01 ; 1 dca: 50 40 sbci r21, 0x00 ; 0 dcc: d8 f7 brcc .-10 ; 0xdc4 dce: 08 95 ret 00000dd0 <__mulsi3>: dd0: ff 27 eor r31, r31 dd2: ee 27 eor r30, r30 dd4: bb 27 eor r27, r27 dd6: aa 27 eor r26, r26 00000dd8 <__mulsi3_loop>: dd8: 60 ff sbrs r22, 0 dda: 04 c0 rjmp .+8 ; 0xde4 ddc: a2 0f add r26, r18 dde: b3 1f adc r27, r19 de0: e4 1f adc r30, r20 de2: f5 1f adc r31, r21 00000de4 <__mulsi3_skip1>: de4: 22 0f add r18, r18 de6: 33 1f adc r19, r19 de8: 44 1f adc r20, r20 dea: 55 1f adc r21, r21 dec: 96 95 lsr r25 dee: 87 95 ror r24 df0: 77 95 ror r23 df2: 67 95 ror r22 df4: 89 f7 brne .-30 ; 0xdd8 df6: 00 97 sbiw r24, 0x00 ; 0 df8: 76 07 cpc r23, r22 dfa: 71 f7 brne .-36 ; 0xdd8 00000dfc <__mulsi3_exit>: dfc: 9f 2f mov r25, r31 dfe: 8e 2f mov r24, r30 e00: 7b 2f mov r23, r27 e02: 6a 2f mov r22, r26 e04: 08 95 ret 00000e06 <__udivmodhi4>: e06: aa 1b sub r26, r26 e08: bb 1b sub r27, r27 e0a: 51 e1 ldi r21, 0x11 ; 17 e0c: 07 c0 rjmp .+14 ; 0xe1c 00000e0e <__udivmodhi4_loop>: e0e: aa 1f adc r26, r26 e10: bb 1f adc r27, r27 e12: a6 17 cp r26, r22 e14: b7 07 cpc r27, r23 e16: 10 f0 brcs .+4 ; 0xe1c e18: a6 1b sub r26, r22 e1a: b7 0b sbc r27, r23 00000e1c <__udivmodhi4_ep>: e1c: 88 1f adc r24, r24 e1e: 99 1f adc r25, r25 e20: 5a 95 dec r21 e22: a9 f7 brne .-22 ; 0xe0e e24: 80 95 com r24 e26: 90 95 com r25 e28: 68 2f mov r22, r24 e2a: 79 2f mov r23, r25 e2c: 8a 2f mov r24, r26 e2e: 9b 2f mov r25, r27 e30: 08 95 ret 00000e32 <__udivmodsi4>: e32: a1 e2 ldi r26, 0x21 ; 33 e34: 1a 2e mov r1, r26 e36: aa 1b sub r26, r26 e38: bb 1b sub r27, r27 e3a: ea 2f mov r30, r26 e3c: fb 2f mov r31, r27 e3e: 0d c0 rjmp .+26 ; 0xe5a 00000e40 <__udivmodsi4_loop>: e40: aa 1f adc r26, r26 e42: bb 1f adc r27, r27 e44: ee 1f adc r30, r30 e46: ff 1f adc r31, r31 e48: a2 17 cp r26, r18 e4a: b3 07 cpc r27, r19 e4c: e4 07 cpc r30, r20 e4e: f5 07 cpc r31, r21 e50: 20 f0 brcs .+8 ; 0xe5a e52: a2 1b sub r26, r18 e54: b3 0b sbc r27, r19 e56: e4 0b sbc r30, r20 e58: f5 0b sbc r31, r21 00000e5a <__udivmodsi4_ep>: e5a: 66 1f adc r22, r22 e5c: 77 1f adc r23, r23 e5e: 88 1f adc r24, r24 e60: 99 1f adc r25, r25 e62: 1a 94 dec r1 e64: 69 f7 brne .-38 ; 0xe40 e66: 60 95 com r22 e68: 70 95 com r23 e6a: 80 95 com r24 e6c: 90 95 com r25 e6e: 26 2f mov r18, r22 e70: 37 2f mov r19, r23 e72: 48 2f mov r20, r24 e74: 59 2f mov r21, r25 e76: 6a 2f mov r22, r26 e78: 7b 2f mov r23, r27 e7a: 8e 2f mov r24, r30 e7c: 9f 2f mov r25, r31 e7e: 08 95 ret