Topic:
Correct understanding of "Set up time" and "Hold time"¡
¡
D flip-flops and
latches are key components in logic design, both sync and async structure.
But sometimes the understanding to these devices is not enough, that will
lead to malfunction in our design. A typical issue we always meet is the
timing relation between edges of clock and data, for example, the CS signal,
data signal and clock signal in a MCU system. Here we will discuss where
the problem is and how can we avoid and overcome these traps ... ...